ID |
Date |
Author |
Subject |
Text |
|
456
|
Sat Dec 5 03:21:21 2015 |
Chris Thompson | PC software beyond Windows 7 | On a hunch, I tried downloading V 5.0.3
instead. This works, and I now have the oscilloscope
mode displaying signals! (just to make sure, |
|
475
|
Thu Jan 14 21:49:37 2016 |
Chris Thompson | Triggering of DRS4 in the fastest sampling mode | I am attempting to use the DRS4 to measure
the timing resolution of a pair of SensL
silicon photomultipliers (SiPM). In order |
|
492
|
Thu Mar 31 20:48:00 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | I needed a fast pulse inverter in order
to feed signals from the recent SensL SiPMs
into a conventional CFD which only accepted |
|
494
|
Fri Apr 1 22:09:07 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | The coilcraft part number is: JA4220-ALB.
Iordered two of them and they were sent as
free samples. You might want to buy some |
|
498
|
Sun Apr 3 22:10:19 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | No there are no other components. I put
a photo of the inverter with its cables SMA
and one end, BNC at the other. You can see |
|
357
|
Fri Jun 27 11:23:19 2014 |
ChengMing Du | drsosc binary to cern ROOT file conversion |
|
|
412
|
Wed May 13 09:31:18 2015 |
Chenfei Yang | transparent-mode voltage | Hello Mr. Stefan Ritt
For DRS4 differential inputs
ranges form 500mV to 1100mV, with ROFS set |
|
414
|
Wed May 13 09:55:09 2015 |
Chenfei Yang | transparent-mode voltage | Here's the problem. My external ADC
has 2Vpp differtial input voltage range.
And the common-mode voltage of the inputs |
|
416
|
Wed May 13 10:27:43 2015 |
Chenfei Yang | transparent-mode voltage | I'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you |
|
418
|
Wed May 13 12:52:22 2015 |
Chenfei Yang | transparent-mode voltage | Yes. I use exactly the same scheme as you
mentioned. I'll try your solution.
|
|
419
|
Wed May 13 16:13:07 2015 |
Chenfei Yang | transparent-mode voltage | If using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate? |
|
441
|
Mon Jul 20 09:25:38 2015 |
Chenfei Yang | Measure the time between different samples | Hi,
I have a question using a data acquisition
card base on DRS4 chip. How can I measure |
|
335
|
Tue Apr 15 18:35:41 2014 |
Carlo Stella | drs_exam project fail to compile | Hi,
when I try to compile drs_exam project
my computer give me this output: |
|
341
|
Thu Apr 24 23:03:25 2014 |
Carlo Stella | drs_exam project fail to compile |
|
|
761
|
Sat Jul 13 01:00:15 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello,
I have recently obtained a DRS4
Evaluation Board (V5), but I am unable to |
|
763
|
Mon Jul 15 19:34:25 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello Stefan,
Thanks for the quick reply. The
issue was a faulty SMA connector, should |
|
117
|
Thu Apr 14 18:23:53 2011 |
Bob Hirosky | Fixes to DOScreen.cpp for recent built on linux | Hello,
I was just building version 3.1.0 and ran |
|
237
|
Thu Apr 11 22:41:13 2013 |
Bill Ashmanskas | code/details for optimal DRS4 timing calibration? | Hi Stefan,
Is either some example code or a
detailed written description available for |
|
768
|
Mon Aug 19 23:01:22 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Hi Stefan,
We have for some time now been
using custom firmware on a custom board to |
|
770
|
Tue Aug 20 16:05:21 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Aha -- many thanks. I think what
tripped up my test logic is that the "done"
state in drs4_eval5_app.vhd that executes |
|