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Thu Jan 1 01:00:00 1970
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ID
Date
Author
Subject
Text
455
Sat Dec 5 02:39:20 2015
Chris Thompson
PC software beyond Windows 7
456
Sat Dec 5 03:21:21 2015
Chris Thompson
PC software beyond Windows 7
475
Thu Jan 14 21:49:37 2016
Chris Thompson
Triggering of DRS4 in the fastest sampling mode
492
Thu Mar 31 20:48:00 2016
Chris Thompson
Trigger on the And of a positive and negative signal
494
Fri Apr 1 22:09:07 2016
Chris Thompson
Trigger on the And of a positive and negative signal
498
Sun Apr 3 22:10:19 2016
Chris Thompson
Trigger on the And of a positive and negative signal
357
Fri Jun 27 11:23:19 2014
ChengMing Du
drsosc binary to cern ROOT file conversion
412
Wed May 13 09:31:18 2015
Chenfei Yang
transparent-mode voltage
414
Wed May 13 09:55:09 2015
Chenfei Yang
transparent-mode voltage
416
Wed May 13 10:27:43 2015
Chenfei Yang
transparent-mode voltage
418
Wed May 13 12:52:22 2015
Chenfei Yang
transparent-mode voltage
419
Wed May 13 16:13:07 2015
Chenfei Yang
transparent-mode voltage
441
Mon Jul 20 09:25:38 2015
Chenfei Yang
Measure the time between different samples
335
Tue Apr 15 18:35:41 2014
Carlo Stella
drs_exam project fail to compile
341
Thu Apr 24 23:03:25 2014
Carlo Stella
drs_exam project fail to compile
761
Sat Jul 13 01:00:15 2019
Brendan Posehn
Evaluation Board Test Functionality
763
Mon Jul 15 19:34:25 2019
Brendan Posehn
Evaluation Board Test Functionality
117
Thu Apr 14 18:23:53 2011
Bob Hirosky
Fixes to DOScreen.cpp for recent built on linux
237
Thu Apr 11 22:41:13 2013
Bill Ashmanskas
code/details for optimal DRS4 timing calibration?
768
Mon Aug 19 23:01:22 2019
Bill Ashmanskas
should one deassert DENABLE while writing the write-shift register?
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