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Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem         Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem         Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem     Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?        Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register?        Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?    Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?        Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode?    Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps?        Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps?    Mon Nov 18 15:49:01 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis        Mon Nov 18 16:00:26 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis        Mon Dec 16 11:09:25 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis        Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis    Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer        Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer        Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer        Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer        Fri Jun 7 11:44:17 2013, tmiron alon, thank you    Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s

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