 Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Dear sir,
We have two evaluation boards of DRS4. We would like to use 8 inputs to be recorded on a trigger and we would like to find the relative time difference
of inputs. So is it possible to synchronize the sampling frequency of the two evaluation boards. |
 Sat Feb 19 22:46:35 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards
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S S Upadhya wrote:
Dear sir, |
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Mon Feb 21 08:10:31 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards
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Stefan Ritt wrote:
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Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Stefan Ritt wrote:
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Mon Oct 14 09:32:33 2019, Danyang, how to acquire the stop position with channel cascading 
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Hi Steffan,
In DSR4 DATASHEET Rev.0.9 Page13, there is a paragraph "If the DRS4 is configured for channel cascading
or daisy chaining, it is necessary to know which the current channel is where the sampling has been stopped. This can be |
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Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading
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You first set A3-A0, on the next clock cycle you issue pulses on srclk, and about 10ns after each clock pulse the output shows up at srout. Best is to
verity this with an oscilloscope.
The radout of the shift register is independent of the readout mode, so you can use with with MUXOUT as well. |
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Mon Oct 14 11:45:06 2019, Danyang, how to acquire the stop position with channel cascading
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I tried the logic in my designed board. The results are shown in the picture: Srout keeps low when A3-A0 is
set to 1101 and srclk is set as you mentioned. And the drs4 chip does not output sine wave in such configuration.
Srout signal only reacts after the rsrload signal is pulled high and A3-A0 is not 1101. |
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Mon Oct 14 12:56:13 2019, Stefan Ritt, how to acquire the stop position with channel cascading
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Note that you have to read out the Write Shift Register only if you do channel cascading, e.g. configuring the chip with 4x2048 bins by setting the Write
Shift Register to 01010101b. Then the Write Shift Register tells you in which 1024-bin segment the Domino Wave has been stopped. If you use the normal
8x1024 bin mode, you don't have to read out the Write Shift Register since it continas only 1's. |
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Mon Oct 14 13:44:26 2019, Danyang, how to acquire the stop position with channel cascading
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Yes, firstly I configured the chip with 4x2048 bins by setting the Write Shift Register to 01010101b， A3-A0 keeps 1101----> secondly
I enabled the domino wave, wait some time for stable, A3-A0 keeps 1111 ---->thirdly stops the domino wave when the trigger comes,
A3-A0 keeps 1101 (or 1010, 0000)----> forthly send the clock pulse to the srclk pin, A3-A0 keeps 1101, srout |
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Mon Oct 14 15:27:09 2019, Stefan Ritt, how to acquire the stop position with channel cascading
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If you configure the Write Shift Register with 01010101b, then all you have to do after a trigger is to set A3-A0 to 1101. The WSROUT pin shows you then
either ther state 01010101b or 10101010b, you the pin should be 1 or 0, and that's all you need. The Write Shift Register is NOT routed to the SROUT
pin, you only see it at the WSROUT pin. |
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Tue Oct 15 08:14:17 2019, Danyang, how to acquire the stop position with channel cascading
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Thanks a lot. The problem is solved when A3-A0 is set 1101 and srclk keeps low.
Best Regards,
Danyang |
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Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
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Hi Steffan,
I have a question about how to acquire the stop channel:
Process: Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, |
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Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading
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The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what
could be wrong:
Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern |
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Fri Nov 5 01:10:25 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
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Jiaolong
wrote:
Hi Steffan, |
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Fri Nov 5 01:12:10 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
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Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.
Stefan
Ritt wrote:
The problem must be on your side, since the Write Shift Register readout |
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Wed Nov 6 11:53:28 2013, Dmitry Hits, flickering screen for drsosc
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Hi,
I have install drs software on ASUS EeeBox with Ubuntu 12.04 LTS. When I try to use ./drsosc the oscilloscope window flickers. Can you suggest |
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Wed Nov 6 12:25:31 2013, Stefan Ritt, flickering screen for drsosc
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Dmitry Hits wrote:
Hi, |
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Mon Nov 18 11:20:15 2013, Dmitry Hits, flickering screen for drsosc
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Stefan Ritt wrote:
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Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter
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Hi all
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Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter
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lorenzo neri wrote:
Hi all |