ID |
Date |
Author |
Subject |
Text |
 |
|
781
|
Wed Oct 23 17:56:26 2019 |
John Jendzurski | Computing corrected time from binary data...what is t_0,0? | In the equations for computing the corrected
time for channels other than channel 1, does
anyone know what the term t0,0 refers |
|
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0 |
|
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
|
776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
|
775
|
Mon Oct 14 10:14:46 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | You first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows |
|
|
774
|
Mon Oct 14 09:32:33 2019 |
Danyang | how to acquire the stop position with channel cascading | Hi Steffan,
In DSR4
DATASHEET Rev.0.9 Page13, there is |
|
|
773
|
Fri Sep 13 15:27:41 2019 |
Arseny Rybnikov | Scaler / How to modify the firmware to change the scaler integration time | Hello,
We want to use the inner DRS4 counter(scaler)
within more than the 100ms integration |
|
|
772
|
Tue Aug 27 09:14:03 2019 |
Stefan Ritt | DRS4 | Is a 5 GSPS oscilloscope suitable for use
with Silicon surface barier detectors?
|
|
|
771
|
Tue Aug 27 08:33:22 2019 |
chinmay basu | DRS4 | Is DRS4 suitable for use with Silicon surface
barrier detectors? |
|
|
770
|
Tue Aug 20 16:05:21 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Aha -- many thanks. I think what
tripped up my test logic is that the "done"
state in drs4_eval5_app.vhd that executes |
|
|
769
|
Tue Aug 20 10:44:45 2019 |
Stefan Ritt | should one deassert DENABLE while writing the write-shift register? | Hi Bill,
you keep DENABLE active all the
time to keep the Domino Wave running, but |
|
|
768
|
Mon Aug 19 23:01:22 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Hi Stefan,
We have for some time now been
using custom firmware on a custom board to |
|
|
767
|
Sat Jul 20 12:28:14 2019 |
Stefan Ritt | Trace Impedance | The DRS4 input is high impedance. So if
you like you can terminate it with 100 Ohm
differentially and route it with 100 Ohm. |
|
|
766
|
Fri Jul 19 01:37:09 2019 |
Ismael Garcia | Trace Impedance | When you're refering to laying a 50
Ohm trace, you're referring to the SMA
input and not the interface between the output |
|
|
765
|
Thu Jul 18 11:37:56 2019 |
Stefan Ritt | Trace Impedance | The requiremnet is the same as for any
high speed analog board, there is othing
special with the DRS4. If you want to terminate |
|
|
764
|
Thu Jul 18 01:03:44 2019 |
Ismael Garcia | Trace Impedance |
Hi Steffan,
|
|
|
763
|
Mon Jul 15 19:34:25 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello Stefan,
Thanks for the quick reply. The
issue was a faulty SMA connector, should |
|
|
762
|
Mon Jul 15 17:26:50 2019 |
Stefan Ritt | Evaluation Board Test Functionality | Have you set the trigger correctly to the
channel with your signal, polarity and level?
Do you undersand the difference between normal |
|