Hi
We have some meesurs to show (attached)
- Dtap and Denable
- Dtap+Denable in zoom
- Dtap + Ref+
- Dtap + Dspeed
From the screen shots it can be seen that ref+ is not synchronized with Dtap (PLL not working correctly)
And Dspeed is going done to zero after some time.
In our system Dspeed is shorted to pllout.
So it looks like pllout do not pump the RC filter capacitors.
We tested various value of R and C's.
Also we checked that pllout is sorted to Dspeed.
Thanks, mony
| Stefan Ritt wrote: |
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I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.
Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.
Stefan
| mony orbach wrote: |
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my refclk is 1.25Mhz
what are the inputs and voltage you need to see?
Avdd and Dvdd are 2.5v
Denable is "1" Dwrite "0"
currently i am doing an external reset cycle, after that i am doing the configuration cycle.
should i relay on the internal reset?
the Dtap is toggling for 33.8msec and then just stops.
Thanks, Mony
| Stefan Ritt wrote: |
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No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?
| mony orbach wrote: |
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Hi
the drs4 start to generate Dtap signal after reset and standard configuration.
while in reset Denable and Dwrite are low
after reset we put Denable in high
the Dtap starts to toggle, and the plllck stabilizes on about 1V.
After 40Msec the Dtap stops to toggle and the plllck go to 2.5V
Why do the Domino stop working?
Thanks, Mony
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