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ID Date Author Subject Text Attachments
  828   Wed May 5 10:12:44 2021 Stefan Rittrecording only timestamp and amplitude and/or filesize maximumThe maximum file size depends on the underlying
linux file system. Common values are 4-16
GBytes.
  
  827   Tue May 4 21:18:28 2021 Abaz Kryemadhirecording only timestamp and amplitude and/or filesize maximumHi,

I have been collecting some date
using the DRS4 board at a trigger rate of
  
  826   Fri Apr 9 21:56:54 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Yes, there is some systematic board noise
on this prototype, unfortunately 
  
  825   Fri Apr 9 21:38:59 2021 Stefan RittSpikes/noise sensitive to clock settings?elog:824




  
  824   Fri Apr 9 20:55:28 2021 Stefan RittUnexpected noise in muxout: t_samp related?If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes
  
  823   Fri Apr 9 20:29:45 2021 Sean QuinnSpikes/noise sensitive to clock settings?Dear DRS4 team,

I'm trying to troubleshoot
some odd spike behavior. If I run the ADC
 spikes_16MHz.pngspike_period.pngbetter_spikes_15MHz.pngspike_period_15MHz.png 
  822   Fri Apr 9 20:22:13 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Hi Stefan,

 

Thanks much for the quick reply.
 ex_cal_wave.png 
  821   Wed Apr 7 08:26:12 2021 Stefan RittUnexpected noise in muxout: t_samp related?Dear Sean,

noise in transparent mode comes
from some coupling to your system clock.
  
  820   Wed Apr 7 03:29:39 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Dear DRS4 team,

I'm experiencing some issues
that seem to be isolated to the ASIC, and
 transp_example.PNGtransp_readout_example_noise.PNGdrs_datasheet_fig11.PNGr0_r1_delay.png 
  819   Fri Mar 5 09:39:42 2021 Stefan RittTrouble getting PLL to lockThat probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock
  
  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lockI found the problem, and it had nothing
to do with the CMOS clock input.  As
it turns out, even though I was using the
  
  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lockThats not a simple modification to my PCB,
but I'll give it a try.  Thanks
for your help
  
  816   Fri Feb 26 22:12:58 2021 Stefan RittTrouble getting PLL to lockSounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals
  
  815   Fri Feb 26 21:24:39 2021 Tom SchneiderTrouble getting PLL to lockProbe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases
  
  814   Fri Feb 26 20:32:25 2021 Stefan RittTrouble getting PLL to lockCan you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?

  
  813   Fri Feb 26 18:33:52 2021 Tom SchneiderTrouble getting PLL to lockStefan,

Thanks for responding so quickly. 
Yes I have my clock source going to REFCLK+
  
  812   Fri Feb 26 17:59:14 2021 Stefan RittTrouble getting PLL to lockI guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else!
  
  811   Fri Feb 26 17:05:26 2021 Tom SchneiderTrouble getting PLL to lockHello,

I am working on a custom PCB design
with the DRS4 chip, and I can't get the
  
  810   Fri Feb 26 08:52:50 2021 Stefan RittDRS spike removal for multiple waveformsJust look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid
  
  809   Thu Feb 25 17:56:39 2021 Matthias PlumDRS spike removal for multiple waveformsHi,

Is there a way that someone can
help me and my student to enable RemoveSymmetricSpikes
  
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