Hello,

I own two 2048-bin evaluation boards, bought roughly within one year (I assume no major hardware changes). The slightly newer board (sn 3102) was kept as a spare and it's performance was never fully evaluated after purchase. Now I am comparing the performance of the two boards and the newer one shows worse noise performance, despite calibrations and exactly the same working conditions (the same USB cable and port, floating inputs, firmware rev.).

Do you have any suggestions where to look for the source of such behaviour - both in the electronics and the software?

Thank you in advance for any help.

Krzysztof

PS: Measured the base frequency of the noise to be 1/512 of the sampling frequency (for 4.726 and 4.092 GHz sf). Some FPGA issue?

We are developing a product which uses the DRS4 with DC coupling.  It's works, but you need to pay attention to the common mode voltage etc.

If you're developing your own board, 

What you describe is kind of independent of the DRS4. You can just build it and see if it works before you connect it to the DRS4. I don't see any better solution.

Stefan

Dear Dr. Stefan Ritt,

Thank you for your reply. My previous description was not accurate enough. We plan to modify the design referring to the attached file, and the details are as follows:

We will remove capacitor C2 to make the input DC-coupled. The signal ranging from -1 V to +1 V comes in via J1, then passes through a π-type attenuator to halve the signal amplitude before entering the amplifier. The amplifier gain is set to 2.

We are considering two dual supply options for the THS4508: +3.5 V / -1.5 V or +4 V / -1 V. The output common-mode voltage is set to 1.8 V through the CMOFS pin. After that, the signal goes through a voltage divider with 28 Ω and 22 Ω resistors.

The final signal to DRS4 has a common-mode voltage of about 0.8 V and a differential swing of -440 mV ~ +440 mV, which meets the DRS4 input requirements.

Could you please check if this THS4508 design is reasonable? We would also be grateful for any better suggestions or alternative solutions.

Thanks a lot for your support!

Best regards,

Mingxin Liu

If you DC-couple the THS4508, you risk that it's output goes to the negative rail (in your case -1.5), which would destroy the DRS4 since it's out of its specs. 

To move negative signals into the posive range of 0V to 2.5V (allowed range for DRS4), the only thing I see is AC coupling with properly biasing. I don't understand why you try to do DC coupling, that will not work. Alternatively, you coudl invert your negative signal with a small inverter (usually two passive coils) which would bring a negative signal into a positive range.

Best regards,
Stefan

Dear Dr. Stefan Ritt,

Thank you so much for your detailed and helpful reply. It’s very clear to me now why the standard DRS4 design uses AC coupling, and I appreciate your practical suggestions on biasing and protection.

I have a follow-up question about the THS4508 amplifier I plan to use at the input stage, if you don’t mind. If I want to make the signal path DC-coupled (both input and output), would it be possible to power the THS4508 with dual supplies, e.g., +3.5 V and -1.5 V, so that the input can accept signals in the range of -1 V to +1 V? In this configuration, could the amplifier still achieve a bandwidth of 700–800 MHz, or is that high bandwidth only guaranteed when using a single +5 V supply?

I would really appreciate your insight on this point.

Thanks again for your help and advice!

Best regards,

Mingxin Liu

We do not have any DC-coupled design for the DRS4. The reason for that is that for many applications we use SiPMs, which are directly powered through the DRS4 board. Since the bias voltage of ~50V would kill the DRS4, we always go with AC-coupling. 

The reason the DRS4 evaluation board cannot fully capture signals below -0.5V is the fact that the board only has a single +5V power supply and no +-5V power rails. Having an additional -5V power rail would make the evaluation board too bulky and it could not be powered over USB.

In principle you could bias the point after the AC coupling capacitor to +5V, then you can capture up to -5V signals. Add a divider by two to go up to -10V. But then the input protection diodes won't work as it, you would need some fast 5V zener diodes which open for signals below -5V to protect the following circuitry.

Stefan

Dear Dr. Stefan Ritt,

My name is Mingxin Liu. Our research group has completed a series of experimental measurements based on the available AC-coupled DRS4 evaluation board. Nevertheless, the AC-coupled input topology cannot fulfill our experimental requirements. As shown in the attached file, the existing hardware design fails to fully capture input signals featuring negative DC offset components. For this reason, we are writing to inquire about your officially recommended hardware design specifications or reference documents for DC-coupled DRS4 evaluation boards.

I look forward to any valuable suggestions and replies. Thanks in advance for your kind help.

Best regards,

Mingxin Liu

The DRS4 gets into the "1.8A" state if DSPEED approaches like 0.7V. Then both inverters of the Domino chain are kind of open and a large current flows. In that state, the only way out is a power cycle.

It's however not clear to me how you get there. If DENABLE is low, this should be prevented. Most FPGAs however pull up their pins on power-on, and ony when configured, the pins go low according to the programming. Maybe it's the time during the FPGA boot which is your problem. Some FPGAs can be configured not to do this. I woulld recommend putting VDD analog, VDD digital, DSPEED, DENABLE, FPGA config ready, all on an oscilloscope and watch what happens during power on. The 1.8A state should be prevented by all means since it could damage the chip.

Stefan

Dear Dr. Stefan Ritt,

I am writing to express my sincere gratitude for your continued and prompt responses to our previous inquiries regarding the waveform truncation issue with the DRS4. Your advice and insights have been invaluable throughout this debugging process.

We have now preliminarily identified and resolved the problem. The key observation came when we powered the DRS4 from an independent supply: shortly after power‑up, with both DENABLE and DWRITE pulled low to GND, the VDD rail still drew an abnormally high current (approximately 1.8 A). This indicated that the DRS4 had been unintentionally activated into an abnormal state. While we confirmed with both an oscilloscope and a multimeter that the DENABLE and DWRITE pins remained at a valid low level, we suspected that the chip’s initialization was corrupted, preventing the internal registers from being loaded with their default values.

To address this, we manually reloaded the default register values via the FPGA. After this modification, the waveform truncation phenomenon completely disappeared.

Thus, we conclude that the root cause of the waveform truncation was improper initialization of the DRS4. Going forward, we will continue to improve the hardware conditions to ensure correct initialization of the chip.

Thank you once again, Dr. Ritt, for your active and generous support. We hope that the problem we encountered and the solution we found will be helpful to other DRS4 users and contribute to the healthy development of the DRS4 community.

Not much I can say here. I know that the DRS4 works reliably, since we have an experiment here with 500 chips running since 5 years and we did not observer what you described. Therefore, it must be some subtle detail of your FPGA code or the voltage levels on your board. As I said, what I would do is to get the evaluation abord and copare signals 1:1.

Stefan

Dear Dr.Stefan

Thank you for your detailed response. Following your suggestion, I used an oscilloscope to observe the RSLOAD and SRCLK signals, and they conform to the readout timing described in the datasheet.

I can now confirm that the DRS4 occasionally fails to correctly update the stop position to cell 1023, or the stored waveform from cell 0 to the stop position is corrupted. As a result, part of the waveform comes from the most recent acquisition while the other part comes from an earlier one, causing the truncation I observed. This issue occurs with a certain probability—more than half of the acquisitions still yield complete, continuous waveforms.

Interestingly, when I use the same FPGA code and host software on the DRS4 evaluation board, no truncation occurs at all. I am currently comparing the behavior of the two setups from both hardware and software perspectives. Could you kindly provide some suggestions on further tests I could perform?

Thank you very much for your help.

Best regards,
Qichao Wu

Actually looking at your waveforms again, I think I understand maybe your problem. You stop the DRS4 randomly, but your ROI readout mode does not really work. Seems like you always read from the first cell, or just from a wrong cell. Since your sine wave period is not a multiple of the readout window, you see a phase jump between the beginning of your sampling window and the end of your sampling window. The little spikes before and after the jump are normal, since the first and last samples of the DRS4 readout might have some offset. Check that your FPGA really uses RSLOAD to start the readout, and not the "full readout".

The evaluation board might really help you, since you can compare 1:1 all control signals with yours.

Stefan

Thank you for your prompt reply. We have developed our own DRS4-based hardware and successfully read out all 1024 bins using ROI mode. However, we are encountering the waveform truncation issue mentioned earlier. If possible, we would also like to purchase an evaluation board for reference.

Does this happen with your own hardware or with the DRS4 evaluation board? If it's your own hardware, do you read out all 1024 bins in the ROI mode or only a partial waveforem?

Dear Dr. Stefan Ritt

I am writing to seek your advice regarding an issue I encountered while using the DRS4 chip in ROI (Region of Interest) readout mode to sample waveforms. My name is Qichao Wu, and I have been working with the DRS4 for waveform sampling.

In my setup, I input two identical sine waves (with a period of 250 ns and the same phase) into two different channels of the same DRS4 chip. Ideally, the waveforms acquired from both channels should completely overlap, as shown in Figure 1. However, I occasionally observe that the waveform from one of the channels is truncated. The truncated portion appears to originate from a different segment of the input signal, resulting in only partial overlap between the two channels. This phenomenon is illustrated in Figure 1. Additionally, there are instances where both channels exhibit truncation simultaneously, as depicted in Figure 2.

I have confirmed this issue by observing the truncated waveforms directly on an oscilloscope when the DRS4 is operated in ROI mode. Notably, the truncation points always occur near cell 0 and cell 1023 of the DRS4 switch array.

Could you kindly provide guidance on how to resolve or mitigate this issue? Any suggestions or insights you could offer would be greatly appreciated.

I look forward to your positive response and thank you in advance for your time and assistance.

Best regards,
Qichao Wu

Turns out it was a damaged DRS4 IC.

I ported the drs4_eval5_app code onto our board and observed much the same misbehaviour.  So I bit the bullet and replaced the DRS4 IC, and things are going better.

Some images

Notes:

• top of the puicture shows the logic channels
• Red: SRCLK
• Blue: SRIN
• Green: SROUT
• Orange: normally WSROUT, but swapped to RSRLOAD for last picture

Hello

I'm working to bring up a new capture board using a DRS4 and I'm having a minor problem and a major problem.

Minor problem: if I send a reset signal into the DRS4, the PLL doesn't work right.  If I leave NRSESET pin with a wek pullup (and never 'manually' reset the DRS4) it runs OK.  Is there some minimum time I need to observe between sending a NRESET pulse and setting DENABLE high to start the PLL?

Major problem: I can't get the stop position.

What am I doing?

• Set DENABLE high
• Wait until DRS capture is requested (seconds to minutes)
• Configure Write Shift Register with 0b01010101
• Configure Write Control Register with 0b11111111
• Fill the Read Shift Register with 1024x '0's
• Set DWRITE high
• Await trigger (some milliseconds). During this phase address = 0b1011
• Set DWRITE low
• Wait ~ 40 ns
• Set address = 0b1101
• Wait ~ 150 us
• Pulse RSRLOAD high for 30 ns
• Wait 30 ns
• Sample SROUT to get top bit of Write Shift Register
• Set address = 0b0000
• Wait ~ 350 ns
• Begin clocking out analog samples

What's going wrong?

• When I look at the first 10 bits out of SROUT, I should see stop positions.  However, these bits are almost always zero (I get 7 bits which are always 0 followed by 3 bits which are sometimes ones)
• When I probe the WSROUT pin (and remembering that DWRITE is low at this point), I expected to see a single one bit coming out of the read shift register as I apply 1024 pulses to SRCLK.  Instead, I am seeing two set bits coming out of the read shift register
• When I plot the captured analog waveform it's a mess - it seems like 2 analog output buffers are enabling at once and fighting over the output voltage

Do you have any suggestions or warnings about proper deployment of the RSRLOAD pin?

I left this a bit late in my day for posting, so I'll need to follow up with some 'scope captures tomorrow.

You have to use the software belonging to that board. You cannot use the newest software with an old board. Look here:

  https://www.psi.ch/en/ltp-muon-physics/software-download

So you need teh software version 2.0.

/Stefan