| ID |
Date |
Author |
Subject |
Text |
 |
|
733
|
Mon Feb 4 16:42:08 2019 |
Hans Steiger | Different Distances between the sampling points | Dear All,
with the older software for my
V5 Board i did not have the problem, that |
|
|
732
|
Sat Feb 2 10:10:22 2019 |
Stefan Ritt | Saving Rate (only 15Acq/s) | The reduction of rate is because you save
in XML format, which is an ASCII format,
so human readable, but takes long to write. |
|
|
731
|
Sat Feb 2 00:13:12 2019 |
Hans Steiger | Saving Rate (only 15Acq/s) | Dear All,
when I use my Evaluation Board |
|
|
730
|
Wed Jan 30 17:08:58 2019 |
Stefan Ritt | ROOT Macro for data acquired with the newest software | This one elog:361
should still work.
Stefan |
|
|
729
|
Wed Jan 30 08:02:25 2019 |
Stefan Ritt | DRS4 domino wave stability study | The Domino wave is most stable at 5 GSPS,
slowly degrades down to 3-2 GSPS, and at
1GSPS gets some significant jitter. This |
|
|
728
|
Wed Jan 30 06:51:37 2019 |
Saurabh Neema | DRS4 domino wave stability study | We have been using DRS4 IC in our design
for quite some time and it is giving good
performance. |
|
|
727
|
Tue Jan 29 14:43:44 2019 |
Abaz Kryemadhi | ROOT Macro for data acquired with the newest software | Hello,
Is there a root macro for decoding
binary data acquired with the newest software |
|
|
726
|
Thu Nov 8 12:02:34 2018 |
Davide Depaoli | Timing Issue | Thanks a lot for the quick response.
We will do as you suggest.
|
|
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
|
723
|
Thu Nov 8 09:57:26 2018 |
Stefan Ritt | Pi attenuator on eval board inputs? | The attenuator compensates for the gain
of the buffer which is slightly above one.
In addition, it serves as a "placeholder" |
|
|
722
|
Mon Nov 5 17:17:08 2018 |
Sean Quinn | Pi attenuator on eval board inputs? | Dear DRS4 team,
I am curious about this part of |
|
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|
|
720
|
Wed Sep 26 18:28:20 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I really
appreciate your help.
Thanks! |
|
|
Draft
|
Wed Sep 26 18:25:07 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I
really appreciate your help.
Thanks! |
|
|
718
|
Wed Sep 26 14:44:14 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | The "Trigger OUT" has changed
recently. It goes high on a new trigger,
but then STAYS high until the board has been |
|
|
717
|
Sun Sep 23 02:22:46 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Hello Stefan,
I am using the DRS4 board connected
to a Raspberry PI and through the drsosc |
|
|
716
|
Thu Sep 13 18:09:13 2018 |
Martin Petriska | "Symmetric spikes" fixed | Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
|
|
715
|
Tue Sep 4 13:04:30 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Yes it's possible, but I have to find
time for that. The software of the evaluation
board takes care of the spikes ("remove |
|
|
714
|
Mon Sep 3 11:17:26 2018 |
Martin Petriska | "Symmetric spikes" fixed | Hi,
Is it possible to fix it by FPGA
changes? I see readout cycle (proc_drs_reedout) in |
|