DRS4 Forum
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   +  Reply  Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration 
   +  Reply  Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 
   +  Reply  Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip 
   +  Reply  Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data 
   +  Reply  Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit 
   +  Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Entry  Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010 
   +  Reply  Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output 
   +  Reply  Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello 
   +  Reply  Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM DRS.cppDRS.hdrs4_eval1.mcs
   +  Reply  Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp 
   +  Reply  Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4 
   +  Reply  Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4 qfn76.png
   +  Reply  Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4 
   +  Reply  Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4 
   +  Reply  Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode 
Entry  Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X Makefile
Entry  Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed no_res.png100ohm.png
Entry  Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability vdd_no_cap.pngvdd_470uf.png
Entry  Thu Jul 9 09:11:03 2009, Stefan Ritt, Current problems with drs_exam.cpp 
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