 Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock
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Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?
Tom
Schneider wrote:
Stefan, |
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Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock
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Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.
DTAP decreases from 3MHz to 0 during this time.
I'll try to get something together to show you. |
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Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock
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Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB
trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2
is not really working. |
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Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock
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Thats not a simple modification to my PCB, but I'll give it a try. Thanks for your help
Stefan
Ritt wrote:
Sounds to me like your REFCLK is not getting through or your PLL loop |
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Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock
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I found the problem, and it had nothing to do with the CMOS clock input. As it turns out, even though I was using the default state of the config
register, I still had to write to it after powerup. Once I did that, the PLL locked immediately.
-Tom |
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Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock
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That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros
into the config register, thus disabling the PLL. Shame that I haven't thought of this before.
Stefan |
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Fri Dec 24 03:13:32 2021, Lynsey, Trouble getting PLL to lock
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I also design the circuit myself. Our problem is the same. Can we communicate？
Stefan
Ritt wrote:
I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, |
 Fri Nov 3 12:11:14 2017, Håkan Wennlöf, Triggering using AND
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Hi!
I'm using the DRSOsc program, and I have a question that I need a bit clarified;
When triggering using AND between two channels, am I then triggering on rising/falling edge of both channels, or on the actual values? |
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Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND
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Think about: How would you make a coincidence (AND) between two edges? Since an edge is infinitesimally small, there is no way to make a meaningful coincidence
between edges. Therefore, the DRS4 EB firmware makes a simple AND of levels. If you trigger on rising signals and do an AND, then you get a trigger if
both values are above their threshold. For falling edge trigger (arrow goes down in the trigger configuration) the board triggers when both signals are |
Thu Jan 14 21:49:37 2016, Chris Thompson, Triggering of DRS4 in the fastest sampling mode 
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I am attempting to use the DRS4 to measure the timing resolution of a pair of SensL silicon photomultipliers (SiPM). In order to do this I need to trigger
the DRS4 only when there is a coincidence between the two input signals, and hopefully make histograms of the relative detection times of each detector.
There are two completely separate issues. (1) I think this may just be a labelling error. In the first image (OR_mode_selected) one can clearly |
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Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode
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Hi Chris,
if you ever used an oscilloscope, you might be familar with the button controlling the riger in respect to "risign edge" vs. "falling
edge". I copied the same for the DRS software. So just click on that button: |
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Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND)
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Hello there,
is it possible to setup trigger in double AND configuration (a pair in and or other pair in and).
eg (CH 1 AND CH 2 ) OR ( CH 3 AND CH4) |
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Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND)
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Unfortunately not with the current firmware.
Stefan
Esperienza |
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Thu Mar 31 19:30:26 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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I would like to be able to trigger in this fashon: channel 0 > 0.1 and. channel 1< -0.1, because I have a positive and a negative signal.
Can DRS4 (5) Eval board do this kind of trigger?
Thanks! |
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Thu Mar 31 19:35:06 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
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No. You have to use an inverter for one of your signals.
Stefan
Abaz |
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Thu Mar 31 19:44:38 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Ok, thanks! do you know an easy in-line inverter like mini-circuit or digikey? Can also redesign the detector I gues to produce
positive signals, just it might be easier if there was a simple inverter if you are aware of? thanks Abaz
Stefan |
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Thu Mar 31 20:34:25 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
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Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups
Abaz
Kryemadhi wrote:
Ok, thanks! do you know an easy in-line inverter like mini-circuit |
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Thu Mar 31 20:38:05 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Thanks, that looks just fine.
Stefan
Ritt wrote:
Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups |
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Thu Mar 31 20:48:00 2016, Chris Thompson, Trigger on the And of a positive and negative signal
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I needed a fast pulse inverter in order to feed signals from the recent SensL SiPMs into a conventional CFD which only accepted negative signals. I got
a very small ferite torridal transformer from Coilcraft and wired up to invert signals then inserted into in 50 ohm coax cable and it works fine. These
things cost only a few cents each! |
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Fri Apr 1 01:30:40 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Hi Chris,
I am looking at Sensl SiPMs as well, can you send the part number from Coilcraft?
Thanks! |