| ID |
Date |
Author |
Subject |
Text |
 |
|
720
|
Wed Sep 26 18:28:20 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I really
appreciate your help.
Thanks! |
|
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|
|
911
|
Mon Dec 23 19:31:31 2024 |
Matias Henriquez | Trigger OUT pulse width variable from 100 us up to 100 ms | Given this new scenario, what is the maximum
rate of events that can be processed then
(a rough estimation would be great, 1/2ms?)? |
|
|
764
|
Thu Jul 18 01:03:44 2019 |
Ismael Garcia | Trace Impedance |
Hi Steffan,
|
|
|
765
|
Thu Jul 18 11:37:56 2019 |
Stefan Ritt | Trace Impedance | The requiremnet is the same as for any
high speed analog board, there is othing
special with the DRS4. If you want to terminate |
|
|
766
|
Fri Jul 19 01:37:09 2019 |
Ismael Garcia | Trace Impedance | When you're refering to laying a 50
Ohm trace, you're referring to the SMA
input and not the interface between the output |
|
|
767
|
Sat Jul 20 12:28:14 2019 |
Stefan Ritt | Trace Impedance | The DRS4 input is high impedance. So if
you like you can terminate it with 100 Ohm
differentially and route it with 100 Ohm. |
|
|
800
|
Wed Oct 21 15:03:13 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
I have questions about the timing |
|
|
801
|
Tue Oct 27 13:37:23 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Seiya,
1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure |
|
|
802
|
Tue Oct 27 15:02:09 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
Thank you for your reply. |
|
|
803
|
Tue Oct 27 15:24:38 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | This is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just |
|
|
804
|
Wed Oct 28 04:32:19 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
OK, it's good to hear! Thank you! |
|
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
|
726
|
Thu Nov 8 12:02:34 2018 |
Davide Depaoli | Timing Issue | Thanks a lot for the quick response.
We will do as you suggest.
|
|
|
374
|
Mon Sep 15 16:24:41 2014 |
Hannes Wachter | Timing Calibration Fail | Hi,
has anyone experienced a shutdown
of the DRSosc.exe or DRScl.exe when executing |
|
|
376
|
Mon Sep 22 15:04:37 2014 |
Stefan Ritt | Timing Calibration Fail |
|
|
|
539
|
Wed Oct 5 22:43:29 2016 |
Will Flanagan | Timestamp for each DRS4 waveform | Hi DRS4 Experts,
I have been analyzing DRS4 binary
data with scripts based on Stefan's (very |
|
|
540
|
Thu Oct 6 11:18:05 2016 |
Stefan Ritt | Timestamp for each DRS4 waveform | In the mentioned read_binary.cpp file you
have the line where you read the event header
i = fread(&eh, sizeof(eh), |
|
|
623
|
Wed Jul 12 04:24:39 2017 |
Toshihiro Nonaka | Time resolution between boards | Hello,
I 'm using four evaluation
boards v.3 to construct the multi-board DAQ |
|