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    Reply  Tue Oct 26 23:18:32 2021, Javier Caravaca, Trigger multiple boards independently 
    Reply  Wed Oct 27 08:11:42 2021, Stefan Ritt, Trigger multiple boards independently 
Entry  Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 18:25:07 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Mon Dec 23 19:31:31 2024, Matias Henriquez, Trigger OUT pulse width variable from 100 us up to 100 ms 
Entry  Thu Jul 18 01:03:44 2019, Ismael Garcia, Trace Impedance DRS4_Analog_IN.PNG
    Reply  Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance 
    Reply  Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance 
    Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
Entry  Wed Oct 21 15:03:13 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register drs4_srin_srout_srclk.pdf
    Reply  Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register Screenshot_2020-10-27_at_13.45.39_.png
    Reply  Tue Oct 27 15:02:09 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
    Reply  Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
    Reply  Wed Oct 28 04:32:19 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
Entry  Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue 
    Reply  Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue 
    Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
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