DRS4 Forum
  DRS4 Discussion Forum, Page 17 of 45  Not logged in ELOG logo
    Reply  Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance 
    Reply  Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance 
    Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
Entry  Wed Oct 21 15:03:13 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register drs4_srin_srout_srclk.pdf
    Reply  Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register Screenshot_2020-10-27_at_13.45.39_.png
    Reply  Tue Oct 27 15:02:09 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
    Reply  Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
    Reply  Wed Oct 28 04:32:19 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
Entry  Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue 
    Reply  Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue 
    Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
Entry  Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail 
    Reply  Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail 
Entry  Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform 
    Reply  Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform 
Entry  Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards 
    Reply  Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards 
Entry  Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output 
    Reply  Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output 
Entry  Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset  
ELOG V3.1.5-2eba886