ID |
Date |
Author |
Subject![down down](down.png) |
66
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Tue Apr 13 14:15:16 2010 |
Stefan Ritt | Simple example application to read a DRS evaluation board |
Heejong Kim wrote: |
Stefan Ritt wrote: |
Several people asked for s simple application to guide them in writing their own application to read out a DRS board. Such an application has been added in software revions 2.1.1 and is attached to this message. This example program drs_exam.cpp written in C++ does the following necessary steps to access a DRS board:
- Crate a "DRS" object and scan all USB devices
- Display found DRS boards
- Initialize the first found board and set the sampling frequency to 5 GSPS
- Enable internal trigger on channel #1 with 250 mV threshold
- Start acquisition and wait for a trigger
- Read two waveforms (both time and amplitude)
- Repeat this 10 times
I know that we are still missing a good documentation for the DRS API, but I have not yet found the time to do that. I hope the example program is enough for most people to start writing own programs. For Windows users (MS Visual C++ 8.0) there is a drs.sln project file, and for linux users there is a Makefile which can be used to compile this example program.
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Hi, Stefan,
drs_exam.cpp is working good to read-out one board.
Now I would like to read-out two boards at the same time using the same trigger( external or internal).
I'm trying to understand and modify the original code for control two board.
Meantime, it would be very appreciated if you give any tips for this.
Thanks,
Heejong
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The evaluation boards are not really made for multi-board applications. What you have to do is to maintain an external trigger which synchronizes the boards. So you need:
- two boards connected to two USB ports
- an external flip-flop connected to the two trigger inputs of both boards
If a trigger is sent to the flip-flop, it sends a trigger to both evaluation boards. You poll on one of the boards to see if it has triggered (vis IsBusy()), then you read out both boards. Now you have to reset the external flip-flop somehow from the computer. If you have a CAMAC I/O board or some other means of sending a logical signal to it, that could do the job. From the software point, you get a "DRS" object upon initialization, which contains then two "DRSBoard" objects, over which you can iterate. Look at the "drscl" program from the distribution on how to do that. |
613
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Tue May 30 20:45:30 2017 |
Esperienza Giove | Setting input range | Hello,
is it possible to set a completely negative input range like -1 to 0 or -0.95 to 0.05 ? |
614
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Tue May 30 21:00:26 2017 |
Stefan Ritt | Setting input range | See elog:531
Esperienza Giove wrote: |
Hello,
is it possible to set a completely negative input range like -1 to 0 or -0.95 to 0.05 ?
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615
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Tue May 30 21:22:10 2017 |
Esperienza Giove | Setting input range | Thank you
Stefan Ritt wrote: |
See elog:531
Esperienza Giove wrote: |
Hello,
is it possible to set a completely negative input range like -1 to 0 or -0.95 to 0.05 ?
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50
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Tue Mar 9 23:28:45 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip | Hi Stefan,
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz?
Thanks!
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51
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Wed Mar 10 10:07:28 2010 |
Stefan Ritt | Serial Interface Frequency of the DRS Chip |
Hao Huan wrote: |
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz?
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The reason for the 16.5 MHz is the following:
After each block of 32 bins, the DRS4 chip switches an internal segment, which causes some small spike at the analog output of the chip. This spike is a bit wider than 30ns, so if everything is digitized with 33 MHz, then you see small spiked each 32 cells. The appropriate solution would be to modify the firmware to digitize all cells with 30ns (33 MHz) and all cells with the spike with ~50 ns (20 MHz). If you do the ROI readout mode, you don't know for the first 10 cells if one of them belong to this class, since the cell address takes 10 cycles to be read out. So you would first have to read 10 cells, and then if you realize that one of them is one of the problematic ones (cell number modulo 32 is zero), you have to re-read the first 10 cells, and digitize the problematic cell with a longer settling time. Now this is a bit complicated to implement in the firmware, so I was just too lazy to do it and decided to digitize everything with 16.5 MHz. But if you are worried about the dead time, you should consider implementing the mentioned algorithm. |
55
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Thu Mar 18 21:38:10 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip |
Stefan Ritt wrote: |
Hao Huan wrote: |
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz?
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The reason for the 16.5 MHz is the following:
After each block of 32 bins, the DRS4 chip switches an internal segment, which causes some small spike at the analog output of the chip. This spike is a bit wider than 30ns, so if everything is digitized with 33 MHz, then you see small spiked each 32 cells. The appropriate solution would be to modify the firmware to digitize all cells with 30ns (33 MHz) and all cells with the spike with ~50 ns (20 MHz). If you do the ROI readout mode, you don't know for the first 10 cells if one of them belong to this class, since the cell address takes 10 cycles to be read out. So you would first have to read 10 cells, and then if you realize that one of them is one of the problematic ones (cell number modulo 32 is zero), you have to re-read the first 10 cells, and digitize the problematic cell with a longer settling time. Now this is a bit complicated to implement in the firmware, so I was just too lazy to do it and decided to digitize everything with 16.5 MHz. But if you are worried about the dead time, you should consider implementing the mentioned algorithm.
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Thanks! The suggested algorithm looks promising. However, if the spikes take place only for those specific cells, is it possible to absorb them into the offset calibration? |
56
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Thu Mar 18 22:10:41 2010 |
Stefan Ritt | Serial Interface Frequency of the DRS Chip |
Hao Huan wrote: |
Thanks! The suggested algorithm looks promising. However, if the spikes take place only for those specific cells, is it possible to absorb them into the offset calibration?
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No, since they are not constant. The bus segments charge up between readouts with a time constant of about 0.5s. So if you do the readout with 1Hz event rate and with 100Hz event rate, the peaks will differ by a factor up to 10, so a constant offset correction cannot take care of that. |
866
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Tue Mar 1 19:03:37 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time | Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation? |
869
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Thu Mar 3 16:14:16 2022 |
Stefan Ritt | Scaler issue to evaluate live time | The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50 Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV pulse and your threshold is 200 mV, your scaler rate drops to zero. That can be seen best with the DRSOsc and sliding the trigger value. If you have a 50 Hz pulse with narrow (< us) pulses, things are fine. But if you use a 50 Hz square wave, then you get distorted signals due to the AC coupling which can also be confusing. See for example here: https://www.daqarta.com/dw_gg0o.htm
Keita Mizukoshi wrote: |
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation?
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870
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Fri Mar 4 03:55:33 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time | Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold).
Still, pulse generator rate and DRS4 rate are a bit different more than 10 Hz.
Stefan Ritt wrote: |
The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50 Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV pulse and your threshold is 200 mV, your scaler rate drops to zero. That can be seen best with the DRSOsc and sliding the trigger value. If you have a 50 Hz pulse with narrow (< us) pulses, things are fine. But if you use a 50 Hz square wave, then you get distorted signals due to the AC coupling which can also be confusing. See for example here: https://www.daqarta.com/dw_gg0o.htm
Keita Mizukoshi wrote: |
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation?
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Attachment 1: pulse_example.png
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Attachment 2: rate.png
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874
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Mon Mar 7 16:37:54 2022 |
Stefan Ritt | Scaler issue to evaluate live time | I tried your measurement with the DRSOscilloscope app (see below), and I measure a constant difference of 10 Hz among the whole range of 100 Hz to 3 kHz.
So I don't know what's wrong on your side. Did you try with the oscilloscope app as well? Have you checked your pulse generator? The evaluation board time reference is a quartz with an accuracy of 10^-5, so no way one can get there a difference you see.
Stefan
Keita Mizukoshi wrote: |
Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold).
Still, pulse generator rate and DRS4 rate are a bit different more than 10 Hz.
Stefan Ritt wrote: |
The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50 Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV pulse and your threshold is 200 mV, your scaler rate drops to zero. That can be seen best with the DRSOsc and sliding the trigger value. If you have a 50 Hz pulse with narrow (< us) pulses, things are fine. But if you use a 50 Hz square wave, then you get distorted signals due to the AC coupling which can also be confusing. See for example here: https://www.daqarta.com/dw_gg0o.htm
Keita Mizukoshi wrote: |
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation?
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Attachment 1: Screenshot_2022-03-07_at_16.37.32_.png
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Attachment 2: Screenshot_2022-03-07_at_16.35.44_.png
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773
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Fri Sep 13 15:27:41 2019 |
Arseny Rybnikov | Scaler / How to modify the firmware to change the scaler integration time | Hello,
We want to use the inner DRS4 counter(scaler) within more than the 100ms integration time. We guess that we need to modify the original firmware around this point:
-- Reference clock used for frequency counter
proc_1hzclk: process(I_RESET, I_CLK33)
begin
if (I_RESET = '1') then
drs_1hz_counter(31 downto 0) <= (others => '0');
drs_1hz_clock <= '0';
scaler_reset <= (others => '1');
scaler_ff_reset <= (others => '1');
elsif rising_edge(I_CLK33) then
drs_1hz_counter <= drs_1hz_counter - 1; -- count down
scaler_reset <= (others => '0');
scaler_ff_reset <= (others => '0');
-- toggle refclk if timer expires
if (drs_1hz_counter(drs_1hz_counter'high) = '1') then
drs_1hz_clock <= not drs_1hz_clock;
drs_1hz_counter(31 downto 0) <= X"0016E35F"; -- 1499999, I_CLK33 is actually a 30 MHz clock
scaler_ff_reset <= (others => '1'); -- reset scaler_ff once every 100ms cycle
loop_scaler_reset : for i in 0 to 5 loop
if (scaler_ff(i) = '0') then -- no activity since last cycle?
scaler_reset(i) <= '1'; -- force clear scaler register
end if;
end loop;
if (scaler_ff(0) = '0') then -- no activity since last cycle?
scaler_reset(0) <= '1'; -- force clear scaler register
end if;
end if;
end if;
end process;
Could you please tell us how to modify the firmware to increse the time up to 5 seconds for instance?
Thanks in advance, Arseny |
454
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Thu Nov 26 18:59:27 2015 |
Robert Adams | Saving histogram data | I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips. |
477
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Tue Feb 16 11:21:43 2016 |
Stefan Ritt | Saving histogram data | There is no histogram save functoinality in ther DRSOscilloscope program - on purpose. The board and the software are meant to evaluate the board, not to replace a full DAQ system. If we want to save histograms, you maybe also want to set the range, make cuts, do fits etc. So it would take lots of resources to add all that. Therefore we recommend to use the stand-alone C program drs_exam.cpp to read the board, the you can either do whatever you want in the C program, including saving of histograms. Alternatively, you can use ROOT to analyze binary stored DRS data and do whatever histogram manipulation you want there.
Stefan
Robert Adams wrote: |
I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips.
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478
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Tue Feb 16 11:55:54 2016 |
Martin Petriska | Saving histogram data |
Robert Adams wrote: |
I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips.
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You can use qtpals, there is posibility to save histograms (energy, time diference), only set trigger on channel which you use. https://sourceforge.net/projects/qtpals/files/?source=navbar |
731
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Sat Feb 2 00:13:12 2019 |
Hans Steiger | Saving Rate (only 15Acq/s) | Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. rate with saving is in the range of 14Hz up to 24 Hz.
I normally use the .txt file. I try to use the 5GS/s but also with much lower sampling rate the saving rate is not getting much better.
Is this a problem of my McBook connected to the Evaluation Board?
All the best,
Hans |
732
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Sat Feb 2 10:10:22 2019 |
Stefan Ritt | Saving Rate (only 15Acq/s) | The reduction of rate is because you save in XML format, which is an ASCII format, so human readable, but takes long to write. If you switch to binary format and write on a decent fast hard disk, you should get back to 450 Acq/s.
Stefan
Hans Steiger wrote: |
Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. rate with saving is in the range of 14Hz up to 24 Hz.
I normally use the .txt file. I try to use the 5GS/s but also with much lower sampling rate the saving rate is not getting much better.
Is this a problem of my McBook connected to the Evaluation Board?
All the best,
Hans
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360
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Wed Jul 30 11:38:58 2014 |
Tsutomu Nagayoshi | Sampling speed of DRS4 Board ver4 | Hello!
I have a question concerning the sampling speed of the DRS4 evaluation board.
It is written in the manual that the sampling speed of DRS4 Evaluation Board is supported above 0.7 GHz.
However I was able to set the sampling speed to be 0.5 GHz with the function DRSBpard::SetFrequency(0.5) and realized that DRSBoard::GetTime function fills time array in every 2 ns.
I am wondering if the data taken with 0.5 GHz sampling is reliable or not.
Best regards,
Tsutomu Nagayoshi
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294
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Mon Sep 23 09:22:52 2013 |
Andrzej Rychter | Sampling Frequency: DRS4 eval board | Is it possible to set sampling frequency at 100 MHz in DRS4 eval board? Trying to set 0.1GHz in Osci program results in around 0.7 GHz. In drscl.exe i'm able to set freq at 0.1GHz but calibration is impossible.
Thank For Help!
Andrzej Rychter |
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