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Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state        Wed Jun 26 13:08:42 2019, Stefan Ritt, drs_exam is always reading out a sin wave        Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave        Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality        Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance        Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance        Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register?        Tue Aug 27 09:14:03 2019, Stefan Ritt, DRS4        Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading        Mon Oct 14 12:56:13 2019, Stefan Ritt, how to acquire the stop position with channel cascading        Mon Oct 14 15:27:09 2019, Stefan Ritt, how to acquire the stop position with channel cascading        Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0?        Fri May 22 12:53:33 2020, Stefan Ritt, DRS4 Evaluation board control tool 'drscl' with macro file        Fri May 22 13:24:51 2020, Stefan Ritt, Type check at DOFrame.h in official software        Tue May 26 12:44:16 2020, Stefan Ritt, Domino wave        Mon Aug 31 10:52:42 2020, Stefan Ritt, Dynamic Range Evaluation Board and Software        Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading        Wed Oct 7 10:56:03 2020, Stefan Ritt, External triggering        Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register        Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register

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