 Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output
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Ron Grazioso wrote:
It looks like the pulse is there but there is something corrupting the data only in binary form. |
 Mon Jul 9 14:14:48 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows 
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Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++
with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions
will be helpful. Thank you. |
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Tue Jul 10 13:15:00 2012, Stefan Ritt, Problem compiling drs_exam.cpp on windows
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Ivan Petrov wrote:
Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to |
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Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows
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Stefan Ritt wrote:
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Thu May 12 05:18:47 2016, Yu, Problem For Software Download
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Hi
I can't download the software for windows on this website 'www.psi.ch/drs/software-download', there is some mistake when i
click on download. |
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Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download
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Can you tell me (screendump) what is the problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to
https://www.dropbox.com/sh/qul1cgtm4x7zx13/AADKQ-qGQGdAHPu6OR3vTNY0a?dl=0 |
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Tue Jul 7 16:39:57 2009, Stefan Ritt, Power up problem and remedy
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Maybe some of you have experienced that the DRS4 chip can get pretty hot after power up. After it's initialized the first time, the power consumption
goes back to normal. I finally found the cause of this problem and have a remedy. Here is the new paragraph from the updated data sheet:
During power-up, care has to be taken that the DENABLE and DWRITE signals are low. If not, the domino wave can get started before the power |
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Wed Nov 23 08:17:23 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello,
I was running through a particular binary file containing data taken on all 4 channels of the DRS4 and printing out the value of the first time
sample for each channel (per event). While doing so, I noticed that some of these times were negative. For this dataset, channel 1 was chosen |
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Thu Nov 24 13:24:26 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The code in the macro is correct. The misconception lies in the definition what "sample 0" means. Please view the attached picture. This is
simplified case with a DRS chip with only 8 cells (instead of 1024). There are two events (blue and red). In the first event, the chip is stopped at trigger
cell (tc) 2, in the second case at 5. Since the readout starts with the trigger cell, the first readout sample in the first event belongs to cell #2, the |
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Tue Nov 29 23:19:06 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello Stefan,
Thank you for the excellent explanation and diagram. This part of the code is now much clearer to me.
My other questions pertain to the "trigger cell". Firstly, what precisely does this mean? Moreover, how does the "trigger |
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Wed Nov 30 08:53:58 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The inverter chain in the DRS4 is continously running in a ring. Once you get a trigger, it is stopped. This happens in any of the 1024 cells. The last
cell which sampled a signal plus ne is called "trigger cell". In the previous diagram in event #1, the last cell sampling was "1",
so the trigger cell is "2". In event 2 (red case), the trigger cell is 5. If you would run like this, you see only the part of the waveform BEFORE |
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Fri Dec 9 04:17:46 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello Stefan,
Many thanks for the explanations. You've cleared my confusion in this matter.
Abhishek Rajput |
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Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
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Dear DRS4 team,
I am curious about this part of the circuit: |
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Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
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The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
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Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout
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Dear Dr. Ritt,
In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize
and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted |
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Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout
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Hao Huan wrote:
Dear Dr. Ritt, |
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Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB
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Hi -
I am setting up a new DRS4 rev5 but using drivers and software we were recently using with a Rev4 (with a recent release of the drs4 code, from
mid-2014). |
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Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB
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First of all, you should not use new boards with old software. I try to keep the current software compatible with old boards, but not vice versa. Please
use the DRS.cpp library from the current V5 software, otherwise your time calibration will not work.
If you then do the calibration with the V5 software and the V5 board, you will see that the bin widhts of the DRS chips are not the same. Actually |
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Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces
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Hi,
we modified drs_exam.cpp to read all 4 channels from the DRS4 and apply directly the spike removal (taken from Osci.cpp) during the acquisition
phase. For test purposes, we don't save the data showing spikes and we focus on the data not having spikes (even if at the end we end up having triple |
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Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces
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I note that your peak at zero is exactly twice as high as the bins left and right, so this looks to me like a binning problem in your histogramming.
Maybe your bin #0 goes from -1mV to +1mV, which all other bins are just 1mW wide. Can you check that?
Stefan |