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    Reply  Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout 
Entry  Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB 
    Reply  Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB 
Entry  Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch1.pngzero_peak_after_spike_removal_ch2.pngzero_peak_after_spike_removal_ch3.pngzero_peak_after_spike_removal_ch4.pngzero_peak_after_spike_removal_offset_correction_ch2.png
    Reply  Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces 
    Reply  Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch2_1000_bins.png
    Reply  Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces Screen_Shot_2018-05-04_at_11.36.24_.png
    Reply  Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces 20180508_drs4_drs_exam_1000_events_81_bins_linear.png20180508_drs4_drs_exam_1000_events_81_bins_log.png20180508_drs4_drs_exam_1000_events_23_bins_linear.png20180508_drs4_drs_exam_1000_events_23_bins_log.png
    Reply  Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces 
Entry  Fri Feb 24 17:34:28 2017, Tarik Zengin, Passing parameters to drscl 
    Reply  Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl 
Entry  Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 start_1ghz.png
    Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4 
    Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4 
    Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Entry  Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock 
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