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ID Date Author Subject Text   667   Thu Mar 8 22:54:20 2018 Rodrigo Trindade de Menezes Running drs_example.cpp   906   Thu Feb 22 01:21:11 2024 Rod McInnis Simulation of FPGA   454   Thu Nov 26 18:59:27 2015 Robert Adams Saving histogram data   616   Thu Jun 8 14:26:23 2017 Rebecca Schmitz AND Trigger problems with 2-3 channels   618   Fri Jun 9 09:44:33 2017 Rebecca Schmitz AND Trigger problems with 2-3 channels   908   Tue May 21 18:13:08 2024 Rebecca Hicks Error when running drsosc   792   Tue Jul 28 22:40:44 2020 Razvan Stefan Gornea no board found   145   Thu Jan 26 09:12:03 2012 Ravindra Raghunath Shinde DRS4 Rev2.0 for analog pulse counting   147   Thu Jan 26 09:44:34 2012 Ravindra Raghunath Shinde DRS4 Rev2.0 for analog pulse counting   149   Thu Jan 26 10:05:57 2012 Ravindra Raghunath Shinde DRS4 Rev2.0 for analog pulse counting   572   Mon Nov 28 22:28:34 2016 Randall Gladen Long timing between two channels   395   Fri Jan 16 13:29:05 2015 Rainer Hentges Mac OSX Yosemite 10.10   873   Mon Mar 7 13:38:03 2022 Radoslaw Marcinkowski Problems with DRS4 Evaluation Board after Windows 10 upgrade - share of experiences   889   Wed Sep 7 10:13:41 2022 Prajjalak Chattopadhyay Register status after reset   676   Thu Mar 22 14:36:01 2018 Phan Van Chuan Read the CalibrateWaveform   698   Thu Jun 7 16:27:21 2018 Phan Van Chuan     703   Tue Jun 19 06:42:23 2018 Phan Van Chuan The data acquisition speed   705   Tue Jun 19 12:54:51 2018 Phan Van Chuan The data acquisition speed   895   Sat Oct 22 13:24:20 2022 Phan Van Chuan Channel Cascading Option in the 2048-bin   424   Sun May 24 09:34:27 2015 Peter Steinberg Peculiar behavior of time values for Rev5 DRS4 EB

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