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New entries since:Thu Jan 1 01:00:00 1970
ID Date Authorup Subject Text Attachments
  791   Tue May 26 12:44:16 2020 Stefan RittDomino waveLook at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom.
  794   Mon Aug 31 10:52:42 2020 Stefan RittDynamic Range Evaluation Board and SoftwareYou cannot go below -0.5V for the inputs,
since the board does not have an internal
negative power supply, which would be necessary
  796   Mon Aug 31 17:17:30 2020 Stefan RittChannel CascadingIf you have a board with cascading option,
it should show the "combined" option
in the 2048-bin option enabled (not grayed),
  798   Wed Oct 7 10:56:03 2020 Stefan RittExternal triggeringThe trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise
  801   Tue Oct 27 13:37:23 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Seiya,

1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure
  803   Tue Oct 27 15:24:38 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerThis is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just
  806   Thu Dec 17 11:31:34 2020 Stefan Rittdrs sources on github?Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/

But development kind of stalled, so there
  808   Wed Jan 20 17:37:51 2021 Stefan Rittdrs4 persistenceThe chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software
  810   Fri Feb 26 08:52:50 2021 Stefan RittDRS spike removal for multiple waveformsJust look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid
  812   Fri Feb 26 17:59:14 2021 Stefan RittTrouble getting PLL to lockI guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else!
  814   Fri Feb 26 20:32:25 2021 Stefan RittTrouble getting PLL to lockCan you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?

  816   Fri Feb 26 22:12:58 2021 Stefan RittTrouble getting PLL to lockSounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals
  819   Fri Mar 5 09:39:42 2021 Stefan RittTrouble getting PLL to lockThat probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock
  821   Wed Apr 7 08:26:12 2021 Stefan RittUnexpected noise in muxout: t_samp related?Dear Sean,

noise in transparent mode comes
from some coupling to your system clock.
  824   Fri Apr 9 20:55:28 2021 Stefan RittUnexpected noise in muxout: t_samp related?If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes
  825   Fri Apr 9 21:38:59 2021 Stefan RittSpikes/noise sensitive to clock settings?elog:824

  828   Wed May 5 10:12:44 2021 Stefan Rittrecording only timestamp and amplitude and/or filesize maximumThe maximum file size depends on the underlying
linux file system. Common values are 4-16
  830   Mon Aug 9 12:50:31 2021 Stefan RittC code to read the 4 channel with external triggerSorry the late reply, I was on vacation. 

Here are some answers:

1. I'm sorry I can't help
  834   Sat Sep 18 15:47:50 2021 Stefan Ritthow to acquire the stop channel with 2x4096 cascading The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So
  835   Sat Sep 18 15:48:30 2021 Stefan Rittdrs_exam_multi with non-v4 boards, default configurationHi,

please note the the evaluation
board is what it says, a board to evaluate
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