| ID |
Date |
Author |
Subject |
Text |
 |
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
|
782
|
Fri Oct 25 16:39:07 2019 |
Stefan Ritt | Computing corrected time from binary data...what is t_0,0? | t0,0 refers to the time of cell #0 of channel
#0. So basically you keep channel 0 fixed,
calculate the difference of each channel's |
|
|
786
|
Fri May 22 12:53:33 2020 |
Stefan Ritt | DRS4 Evaluation board control tool 'drscl' with macro file | There is an example program in the distribution
under software/drscl/drs_exam.cpp which is
a stand-alone program to do what you need. |
|
|
788
|
Fri May 22 13:24:51 2020 |
Stefan Ritt | Type check at DOFrame.h in official software | The software is a bit outdated, I will
soon make a new release.
In meantime, you can replace that |
|
|
791
|
Tue May 26 12:44:16 2020 |
Stefan Ritt | Domino wave | Look at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom. |
|
|
794
|
Mon Aug 31 10:52:42 2020 |
Stefan Ritt | Dynamic Range Evaluation Board and Software | You cannot go below -0.5V for the inputs,
since the board does not have an internal
negative power supply, which would be necessary |
|
|
796
|
Mon Aug 31 17:17:30 2020 |
Stefan Ritt | Channel Cascading | If you have a board with cascading option,
it should show the "combined" option
in the 2048-bin option enabled (not grayed), |
|
|
798
|
Wed Oct 7 10:56:03 2020 |
Stefan Ritt | External triggering | The trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise |
|
|
801
|
Tue Oct 27 13:37:23 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Seiya,
1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure |
|
|
803
|
Tue Oct 27 15:24:38 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | This is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just |
|
|
806
|
Thu Dec 17 11:31:34 2020 |
Stefan Ritt | drs sources on github? | Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/
But development kind of stalled, so there |
|
|
808
|
Wed Jan 20 17:37:51 2021 |
Stefan Ritt | drs4 persistence | The chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software |
|
|
810
|
Fri Feb 26 08:52:50 2021 |
Stefan Ritt | DRS spike removal for multiple waveforms | Just look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid |
|
|
812
|
Fri Feb 26 17:59:14 2021 |
Stefan Ritt | Trouble getting PLL to lock | I guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else! |
|
|
814
|
Fri Feb 26 20:32:25 2021 |
Stefan Ritt | Trouble getting PLL to lock | Can you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?
|
|
|
816
|
Fri Feb 26 22:12:58 2021 |
Stefan Ritt | Trouble getting PLL to lock | Sounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals |
|
|
819
|
Fri Mar 5 09:39:42 2021 |
Stefan Ritt | Trouble getting PLL to lock | That probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock |
|
|
821
|
Wed Apr 7 08:26:12 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | Dear Sean,
noise in transparent mode comes
from some coupling to your system clock. |
|
|
824
|
Fri Apr 9 20:55:28 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes |
|