Hello Sir,

Regarding to analog pulse counting by using DRS4 Rev.2.0 board, you have said that "There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months."

I am interested in it. I have DRS4 Rev.2.0 board. I have FPGA and Microcontroller firmware for this board. How can I implement this concept of counting pulses?

Quick question - what type of connectors are used for the trigger and clock in/out on the v4 eval board?

DRS4 is used for PMTs and APDs. The minimal rise/fall time which can be recorded with the DRS4 on the evaluation boards is about 0.8ns (see elog:84). Concerning charge measurement, it depends on your integration time. If your signal is for example 20ns and you sample with 5 GSPS, you get actually 100 samples. You digitize with 12 bits, but the S/N ratio is more like 11.5 bits. But since you have 100 samples, the accuracy of the measurement scales with sqrt(100)=10. So you have more like 11.5+3 bits = 14-15 bits, or a SNR of 20'000. Now your signal usually does not have an amplitude of 1V, will be more like 100mV or so, in which case your SNR goes to 2000. But this still gives you a resolution of 1/2000 = 0.5 per mille.

We did tests with a Ge detector for spectroscopy applications, where we used a shaping time of 2 micro seconds, both with traditional electronics and the DRS4, integrating the signal over 2 micro seconds. Both gave a resolution of about 0.4%, indicating that the resolution was not limited by the DRS but by the detector.

Best regards,

Stefan 

Hello.

We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring.

So we need to know what sort of detectors for physical experiment the DRS4 has been used in?

Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?

Hello,

I'm co-organizing the upcoming Real Time Conference, which covers also fields of waveform processing and sampling, so it might be interesting for people working with the DRS4 chip. If you have recent results, you could also consider to send an abstract to this conference.  It will be nicely located in Berkeley, California. We plan excursions to San Francisco and to Napa Valley.

Best regards,

Stefan Ritt

18th Real Time Conference
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 Thank you very much.

With regards,

Ravindra R. Shinde

I understand that. But still the board has some dead time which is dominated by the USB data transfer speed.

There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months.

Best regards,

Stefan 

 Thanks for your prompt reply.

Along with pulse rate  we also want see pulse shape as well as charge measurements. That is why we are exploring this option with our existing DRS Set-up.

If you just want to count pulses, you do not need a DRS board. Just use a discriminator and a counter, that's much simpler. The DRS board is not dead time free. 

Hello,

We are using DRS4 Rev.2.0 board.

We want to measure number of pulses generated  by charge particle detector. These negative going analog pulses are very fast having rise time about 2nS.

We want keep threshold level to -20mV. We expected pulse rate to be about 100 to 200 Hz.

I need help to implement this in  current DRS board with  dead time free operation.

Hello Stefan,

Thanks for your prompt reply.

drs_exam is working now after modification as above.

By some trials, I found that external trigger is possible by 'b->EnableTrigger(1,0); b->SetTriggerSource(1<<4);'

Best,

Heejong

The issue is that the V4 board has new trigger capabilities (such as coincidences between two channels) which require a slightly different configuration. Here it the new code:

   /* use following lines to enable hardware trigger on CH1 at 50 mV positive edge */
   if (b->GetBoardType() == 8) {     // Evaluaiton Board V4
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source
   } else {                          // Evaluation Board V3
      b->EnableTrigger(0, 1);           // lemo off, analog trigger on
      b->SetTriggerSource(0);           // use CH1 as source
   }

The complete file is attached. Please try again with the new code. Probably next week I will make a new software release (including a Mac version of all programs) which will contain the new code. Sorry for any inconvenience.

Best regards,
Stefan

Hello,

I'm using DRS4 evaluation board version4 in Linux (Scientific Linux 5).

Version4 software (drs-4.0.0) was installed without any troubles.

The oscilloscope interfrace program (drsosc) is working fine with version4 software.

But when I tried drs_exam program, it doesn't work as expected.

(500 mV positive (width 50ns)  pulse is connected to Ch#1).

It keeps waiting trigger in the first event.

In the previous version (board/software drs-3.0.0), drs_exam program worked well.

I'm wondering if anybody is using drs_exam with V4 evaluation board.

Any comments/help would be welcomed.

Thanks,

Heejong

You are right. The SYNCDELAY should contain three wait cycles. I kind of remember that this delay is not very critical. That might be the reason why the system works even with the wrong delay reliably. 

Hi Stefan,

    I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip: on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization as defined in fx2sdly.h should be (3*12000+5*30000-1)/(2*30000)=3, but the actual number used in drs_eval.c is (3*12000+5*48000-1)/(2*48000)=2, so there is a mismatch between the IFCLK frequency used in this calculation and the actual IFCLK frequency configured. Am I misunderstanding something or is there an explanation for that?

    Thanks,

Hao Huan

In the attachement you will find a working DC-coupled input stage to the DRS4 chip. The bandwidth of this design is about 700 MHz, the gain is 1.

The upper version does not have an additional input buffer. This is not a very "clean" design, since the differential driver has an input impedance of 150 Ohm, which together with the 75 Ohm termination resistor gives about 50 Ohm termination. 

The lover version has an additional input buffer, which nicely decouples the input from the differential driver, so a proper 50 Ohm termination can be used at the cost of additional power for that buffer.

The COM common mode voltage and the OFS voltage have to be set according to the required input range, so that ranges such as 0V...1V, -0.5V...+0.5V, -1V...0V can be used. The COM voltage can be high impedance (simple resistor divider), while the OFS voltage needs to be low impedance (fast active buffer). The analog switch ADG918 can be used to digitize a precise calibration voltage CAL+, which can then be used for precise gain calibration of the DRS4 sampling cells.

> I was just building version 3.1.0 and ran into some problems in DOScreen.cpp.  Basically the conversions from
> char* to wxString were generating "ambiguous overload" errors (in gcc 4.4.3, wx-2.8)
> 
> The simple fix is given in  the following diff output.

Today, I ran into the same problem and was happy to find your fix. I've incorporated it into a unified diff file,
that can easily be applied with the patch program by saving it into a file ('drsosc-3.1.0-wxfix.patch', say), and
in the drs-3.1.0 directory running:

patch -1 < drsosc-3.1.0-wxfix.patch

This is the file:

--- src/DOScreen.cpp.orig	2011-12-09 15:49:48.682201902 +0100
+++ src/DOScreen.cpp		2011-12-09 15:51:45.666000111 +0100
@@ -234,7 +234,7 @@ void DOScreen::DrawWaveform(wxDC& dc, wx
 
    // display optional debug messages
    if (*m_frame->GetOsci()->GetDebugMsg()) {
-      wxst = m_frame->GetOsci()->GetDebugMsg();
+      wxst = wxString(m_frame->GetOsci()->GetDebugMsg(),wxConvUTF8);
       dc.SetPen(wxPen(*wxLIGHT_GREY, 1, wxSOLID));
       dc.SetBrush(*wxGREEN);
       dc.SetTextForeground(*wxBLACK);
@@ -243,7 +243,7 @@ void DOScreen::DrawWaveform(wxDC& dc, wx
       dc.DrawText(wxst, m_x1+4, m_y1+2);
    }
    if (m_debugMsg[0]) {
-      wxst = m_debugMsg;
+      wxst = wxString(m_debugMsg,wxConvUTF8);
       dc.SetPen(wxPen(*wxLIGHT_GREY, 1, wxSOLID));
       dc.SetBrush(*wxGREEN);
       dc.SetTextForeground(*wxBLACK);
@@ -474,9 +474,9 @@ void DOScreen::DrawWaveform(wxDC& dc, wx
    if (m_osci->GetNumberOfBoards() && m_osci->IsIdle()) {
       dc.SetTextForeground(*wxGREEN);
       if (m_osci->GetTriggerMode() == TM_AUTO)
-         wxst = "AUTO";
+         wxst = wxString("AUTO",wxConvUTF8);
       else
-         wxst = "TRIG?";
+         wxst = wxString("TRIG?",wxConvUTF8);
       dc.GetTextExtent(wxst, &w, &h);
       dc.DrawText(wxst, m_x2 - w - 2, m_y1 + 1);
    }

The evaluation board has a 50 Ohm termination resistor, which already converts your current into a voltage signal. If the resulting signal is too low (<20 mV) you can put in an amplifier or raise the HV of your PMT (inside the valid range given by its datasheet of course).

- Stefan 

I want to measure the signal from PMT . But it is a current signal, should i just put a series resistance, or use a amplifier to convert it to voltage signal before drs4?  

Can you give me some advice ? 

Good questions. I looked myself in the code and found:

  drs_readout_clk       <= I_CLK33;

  drs_readout_clk_ps    <= I_CLK33; -- phase shifted clock for FADC

  drs_serial_clk        <= I_CLK33;

which is apparently wrong (should be drs_readout_clk_ps <= I_CLK33_PS;) . But apparently the board is working with the unshifted clock. Could be that the PCB traces to the DRS and the ADC have different lengths, and by accident, they have just the right value.

The way to find that out is to keep the ADC clock phase variable (most FPGAs allow a +-5 ns phase adjustment inside their clock blocks), and then try different values. If the phase shift is wrong, you will see spikes every 32 samples in the readout. The spikes are always there (from some internal switching of bus segments), and you can see them with a differential probe at the DRS output. The ADC phase must then be made such that the sampling point of the ADC comes after that spike, just at the end of the settling time, barely before the next analog value shows up at the DRS output. This is a bit tricky and can be made best just by trying out different values.