 Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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(Board Type:9, DRS4)
Hello,
I´m trying to reach the timig resolution of about 2.5ps as written in the manual. |
 Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Can you post a screenshot of your measurement?
Stefan
Danny |
Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
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Hello Stefan,
Chn2 & Chn3 were used for delay-determination as you can see on the second picture.
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Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Ok, I got it. The timing resolution is affected by the signal-to-noise ratio over the rise-time of your signal. You find the full formula herer:
https://arxiv.org/abs/1405.4975
Your sine wave input signal has a slow rise time, and therefore limits the time resolution. I reproduced your measurement with a 20 MHz sine |
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Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Hello Stefan,
thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my
function generator). |
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Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker at the
very left side of the screen, where the yellow marker is at a different position as the others. Hint: a right-click on that slider sets it to zero. The
little streak could be some kind of external noise. |
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Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker |
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Fri Jun 7 11:44:17 2013, tmiron alon, thank you
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Stefan Ritt wrote:
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Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
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Hi everyone,
Has anyone tried to synchronize 2 (two) DRS4 evaluation boards readout by the same computer? I have read about some attempts on this board in the
past, but I do not know if they have succeeded. If yes, could you share your experience and/or software. |
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Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer
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Dmitry Hits wrote:
Hi everyone, |
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Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
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Stefan Ritt wrote:
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Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer
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Dmitry Hits wrote:
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Mon Nov 18 15:49:01 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
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Dear Stefan,
I am trying to synchronise the readout of two test boards, one is the DRS4 test board, the other is PSI46 test board (used for the readout of CMS
pixel chip) for the offline analysis. I think that the most secure way to accomplish this is to pass a trigger number from one test board to the other. |
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Mon Nov 18 16:00:26 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
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Dmitry Hits wrote:
Dear Stefan, |
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Mon Dec 16 11:09:25 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
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Stefan Ritt wrote:
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Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
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Dmitry Hits wrote:
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Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps?
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Dear DRS4 community,
Is there a way to extract timestamps with sub-ms precision? The milliseconds of an event is clearly given when unpacking the header. I would
like to determine how far apart events are when they are within the same millisecond. |
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Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps?
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Putting sub-ms precision into the header does not make sense, since the USB transfer only happens in time-slots of about 2 ms. To get better timing,
you would need a hardware time clock in the FPGA, which does not exist right now.
Best, |
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Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?
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Hello!
We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about
dead-time. with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet. |
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Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode?
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Benjamin LeGeyt wrote:
Hello! |