 Mon Dec 3 09:18:09 2012, Stefan Ritt, Another question about using multi boards.
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Gyuhee Kim wrote:
Hi. |
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Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards.
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Stefan Ritt wrote:
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 Wed Jan 15 14:20:51 2014, Stefan Ritt, Announcement of new Evaluation Board V5 
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Dear DRS community,
starting from this year, we ship the new evaluation board V5. This board has an improved internal timing calibration, with which one can measure
the time with a precision down to a few ps. Following picture shows the time between two pulses, obtained with a function generator, a passive split and |
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Tue Feb 18 14:12:37 2014, Stefan Ritt, Announcement of new Evaluation Board V5
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Stefan Ritt wrote:
Dear DRS community, |
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Mon Jun 9 12:03:26 2014, Osip Lishilin, Announcement of new Evaluation Board V5
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Stefan Ritt wrote:
Hardware scalers for all four channels and the trigger working up to 200 MHz. With the trigger scaler |
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Wed Jun 11 11:13:50 2014, Stefan Ritt, Announcement of new Evaluation Board V5
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Osip Lishilin wrote:
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Mon Jun 16 15:35:59 2014, Osip Lishilin, Announcement of new Evaluation Board V5
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Stefan Ritt wrote:
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Mon Jul 12 16:07:37 2010, Stefan Ritt, Announcement evaluation board V3
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Dear DRS4 users,
a new version of the evaluation board has been designed and is in production now. The main difference is that it uses active input amplifiers,
which result in an analog bandwidth of 700 MHz (as compared with the 220 MHz of the previous board) at moderate power consumption, so the board can still |
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Fri Feb 25 10:13:51 2011, Stefan Ritt, Announcement digital pulse processing workshop
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Dear colleague,
if you live not so far from Zurich, you might be interested in this workshop:
http://www.xtronix.ch/hep/psi_workshop.htm |
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Mon Apr 27 15:09:49 2009, Stefan Ritt, Amplitude and Timing calibration for DRS4 Evaluation Board
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This is a quick notification to all users of the current DRS4 evaluation board.
As you all know, the DRS4 chip needs some calibration for each individual cell which corrects the offset and the non-equidistant width in time.
While the first evaluation boards have been shipped without this calibration, the current version of the software implements a full amplitude and timing |
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Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems
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Dear Stefan,
I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals
are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude |
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Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems
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In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than
4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in
the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if |
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Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
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Hello,
I work with the DRS4 Evaluation Board V5 and I have a problem with the software.
I have a problem with |
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Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?
Stefan
Rebecca |
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Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
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Hello,
It seems that a coincidence with two fixed channels suddenly works. I don't know why.
Screenshot 1 shows the trigger settings for the coincidence with two channels. |
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Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Hi,
from our screenshots I see the following:
- you have sometimes a huge oscillation in your preamplifier. Fix this first before doing any waveform recording |
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Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables
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Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).
Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay
cable? |
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Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables
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Martin Petriska wrote:
Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048). |
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Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |