DRS4 Forum
  DRS4 Discussion Forum, Page 3 of 15  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
   +  Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
   +  Reply  Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality 
   +  Reply  Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
   +  Reply  Wed Jun 26 15:17:51 2019, Si Xie, Running drs_example.cpp 
   +  Reply  Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state 
   +  Reply  Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board 
Entry  Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit 
Entry  Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software read_binary.C
Entry  Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs 
   +  Reply  Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points 
   +  Reply  Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s) 
   +  Reply  Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software 
   +  Reply  Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study 
   +  Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
   +  Reply  Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs? 
   +  Reply  Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
   +  Reply  Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed 
   +  Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
   +  Reply  Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support 
   +  Reply  Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing 
ELOG V3.1.4-bcd7b50