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Tue Nov 19 04:33:22 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks        Tue Nov 19 21:49:37 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks    Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root    Mon Sep 23 09:22:52 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board        Mon Sep 23 09:51:48 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board    Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X    Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time    Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate    Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock    Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?    Thu Apr 11 22:41:13 2013, Bill Ashmanskas, code/details for optimal DRS4 timing calibration?    Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?        Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?    Thu Apr 14 18:23:53 2011, Bob Hirosky, Fixes to DOScreen.cpp for recent built on linux    Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality        Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality    Tue Apr 15 18:35:41 2014, Carlo Stella, drs_exam project fail to compile        Thu Apr 24 23:03:25 2014, Carlo Stella, drs_exam project fail to compile    Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage        Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage

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