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ID
Date
Author
Subject
Text
105
Mon Jul 19 12:47:17 2010
Stefan Ritt
Fixed Patter Timing Jitter
104
Mon Jul 19 12:07:04 2010
Jinhong Wang
Fixed Patter Timing Jitter
Hi Stefan, can you give some suggestions
on determination of fixed pattern timing
jitter of DRS4? Thanks~
99
Mon Jul 12 16:07:37 2010
Stefan Ritt
Announcement evaluation board V3
Dear DRS4 users,
a new version of the evaluation board
has been designed and is in production now.
98
Tue Jun 22 11:37:42 2010
Jinhong Wang
Reset of DRS4
97
Tue Jun 22 11:35:18 2010
Stefan Ritt
Reset of DRS4
96
Tue Jun 22 11:29:26 2010
Jinhong Wang
Reset of DRS4
95
Tue Jun 22 11:02:30 2010
Stefan Ritt
Reset of DRS4
94
Tue Jun 22 10:50:19 2010
Jinhong Wang
Reset of DRS4
Hi Stefan,
I found
DRS draw a lot of current when applied Reset
93
Sat Jun 19 10:09:18 2010
Jinhong Wang
DVDD Problem of DRS 4
92
Fri Jun 18 11:45:18 2010
Stefan Ritt
DVDD Problem of DRS 4
91
Fri Jun 18 11:31:20 2010
Jinhong Wang
DVDD Problem of DRS 4
88
Tue Jun 1 13:36:18 2010
Stefan Ritt
High Frequency Input for DRS
87
Wed May 26 19:18:09 2010
Hao Huan
High Frequency Input for DRS
Hi Stefan,
I read in the
DRS datasheet that the bandwidth for the
86
Wed May 19 09:16:02 2010
Stefan Ritt
DVDD Problem of DRS 4
85
Wed May 19 02:24:12 2010
Hao Huan
DVDD Problem of DRS 4
84
Tue May 18 09:24:02 2010
Stefan Ritt
Reference design for DRS4 active input buffer
The design of high frequency differential
input stages with the DRS4 is a challenge,
since the chip draws quite some current at
83
Tue May 18 08:23:07 2010
Stefan Ritt
DVDD Problem of DRS 4
82
Tue May 18 01:47:59 2010
Hao Huan
DVDD Problem of DRS 4
81
Fri May 14 08:40:14 2010
Stefan Ritt
DVDD Problem of DRS 4
80
Thu May 13 19:14:27 2010
Hao Huan
DVDD Problem of DRS 4
Hi Stefan,
on our board some
DRS chips draw a lot of current through DVDD
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