 Sun Apr 3 22:10:19 2016, Chris Thompson, Trigger on the And of a positive and negative signal 
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No there are no other components. I put a photo of the inverter with its cables SMA and one end, BNC at the other. You can see it is very small. I glued
the inverter to a piece of thin plywood, and fixed the cables to it before attempting to solder them to the pads on the ferite bead support
Abaz |
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Fri Jun 27 11:23:19 2014, ChengMing Du, drsosc binary to cern ROOT file conversion
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Stefan Ritt wrote:
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 Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage
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Hello Mr. Stefan Ritt
For DRS4 differential inputs ranges form 500mV to 1100mV, with ROFS set to 1.55V, O_OFS set to 1.3V, the outputs of DRS4 is shown in the
attachment. |
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Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage
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Here's the problem. My external ADC has 2Vpp differtial input voltage range. And the common-mode voltage of the inputs need to be 1.3V. I cannot
make both the transparent-output and the readout-output meet the ADC input requirement.
Stefan |
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Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage
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I'm using an AD9252, 0.9V common mode voltage is suggested and I already use 8 un-switchable level shifters. Just as you said, this common mode range
is recommended for optimum performance and the device can function over a wider range with reasonable performance. So I think I could
adjust O_OFS to a minor level during transparent output. |
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Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage
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Yes. I use exactly the same scheme as you mentioned. I'll try your solution.
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
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Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage
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If using a ROFS of 0.9V, the input would not between 1.05V~2.05V better non-linearity area. Is that appropriate?
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
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Mon Jul 20 09:25:38 2015, Chenfei Yang, Measure the time between different samples
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Hi,
I have a question using a data acquisition card base on DRS4 chip. How can I measure the time between several samples of one channel，with the
accuracy of like nanoseconds , for I am using the internal trigger. Is there any complete work about this problem？
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Tue Apr 15 18:35:41 2014, Carlo Stella, drs_exam project fail to compile
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Hi,
when I try to compile drs_exam project my computer give me this output:
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Thu Apr 24 23:03:25 2014, Carlo Stella, drs_exam project fail to compile
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Stefan Ritt wrote:
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Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello,
I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There
seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or |
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Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello Stefan,
Thanks for the quick reply. The issue was a faulty SMA connector, should have checked this first. Signal looks good now.
Thanks for your time, |
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Thu Apr 14 18:23:53 2011, Bob Hirosky, Fixes to DOScreen.cpp for recent built on linux
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Hello,
I was just building version 3.1.0 and ran into some problems in DOScreen.cpp. Basically the conversions from
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Thu Apr 11 22:41:13 2013, Bill Ashmanskas, code/details for optimal DRS4 timing calibration?
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Hi Stefan,
Is either some example code or a detailed written description available for the improved DRS4 timing-calibration algorithm described by Daniel
Stricker-Shaver at MIC 2012? I think you told me that you had verified the results with your own test set-up, so I figure there must be at least |
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Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
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Hi Stefan,
We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips. Now we are working on cascaded
readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency. |
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Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
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Aha -- many thanks. I think what tripped up my test logic is that the "done" state in drs4_eval5_app.vhd that executes post-readout sets
DWRITE back to 1 (drs_write_set). If one then writes to FPGA register 5 while the FSM is in the "idle" state, the conf_strobe and wsr_strobe
states occur with DWRITE and DENABLE both asserted. This is if one sets the "dactive" bit in the FPGA app code, which is probably not the |
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Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock
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Hello!
let me apologize in advance if this has already been covered somewhere and I missed it.
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Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?
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Hello!
We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about
dead-time. with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet. |
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Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate
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Hi,
Our setup uses a DRS4 evaluation board (version 2.0).
Although we trigger the board at a rate of ~4kHz (on channel2), readout through USB2 is only happening at a rate of ~125Hz. |
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Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time
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Hello,
We want to use the inner DRS4 counter(scaler) within more than the 100ms integration time. We guess that we need to modify the original
firmware around this point: |