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Entry  Fri Aug 7 18:41:37 2015, dante, DRS4 

Hi

I have just installed DRS4, but when I try to view it from the USB it don't work. Why?

 

  [  .../home  $] lsusb -d 04b4:1175 -v

Bus 002 Device 008: ID 04b4:1175 Cypress Semiconductor Corp.
Couldn't open device, some information will be missing
Device Descriptor:

Entry  Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware 

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point? Or is there any drs4_eval4_app.vhd missing in the source files?

 

thanks

 

Hongwei

    Reply  Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware 

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

    Reply  Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware 

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

    Reply  Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware 

Stefan Ritt wrote:

hongwei yang wrote:

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

 Here it is.

 Thanks. have a good day

Entry  Tue Dec 10 14:48:42 2013, ismail okan atakisi, measurement range 

I m trying to measure lifetime in our lab and I intend to take
measurement with DRS4 at that point I have a little bit confused about
DRS4 time range.In My system I opened 10 us gate but after triggering
DRS4 measure nearly 1.2 us. Because of this I want to extend DRS4 time range that
measurement range from 1.2us to 10 us.  

Entry  Tue Aug 27 16:14:49 2013, lengchongyang,  

  Hello everyone!I'm a new user of DRS4 board,but it seems that some files are missing in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!

T

 

    Reply  Wed Aug 28 04:05:48 2013, lengchongyang,  

lengchongyang wrote:

  Hello everyone!I'm a new user of DRS4 board,but it seems that some files are missing in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!

T

 

 I checked my project today and I think I need the file USR_LIB_VEC_IOFD_CPE_NALL.I don't know if is it a VHD files or a IP core.

I'll be extremely grateful.

Entry  Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter 

Hi all



it is possible to use the evaluation board like a counter?



I'm interested in the arriving time of all self trigger event in to a channel.



the input signal are 2V TTL of 10 ns at 50ohm, and the time acquisition window is 1 second.




can someone help me?



thanks in advance,



Lorenzo

Entry  Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec 

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

    Reply  Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec 

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

    Reply  Sun Dec 27 15:06:59 2015, mony orbach, Dtap stops toggling after 40msec 

Hi

We have some meesurs to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Ref+
  4. Dtap + Dspeed

From the screen shots it can be seen that ref+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

Stefan Ritt wrote:

I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.

Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.

 

Stefan

 

mony orbach wrote:

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

 

 

    Reply  Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec Dtap-Denable.gifdtap-Danable2.gifDtap-refck.gifDtap-Dspeed.gif

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

Stefan Ritt wrote:

I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.

Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.

 

Stefan

 

mony orbach wrote:

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

 

 

    Reply  Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec 

Hi Stefan

Thanks for your input.

We are in the process of assemble another PCB board.

so soon we can compere between two boards.

As for the PLLEN bit, we set it.

We checked several times the soldering of the DRS4 using a microscope.

Everything looks ok.

In what method do you recommend to solder the DRS4?

 

Thanks for the invitation to meet.

120Km is not so far J

 

mony

Stefan Ritt wrote:

Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.

Stefan

mony orbach wrote:

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

    Reply  Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec 

Hi

We have resolve the problem, the Dtap is now working correctly.

There were two problems:

  1. After configuration we put the all address bits to one (standby mode)

We are now setting the address bits to all zero. Failure

to do so result in Dtap  stop toggling after several hundred milliseconds.

  1. The DMODE bit in contradiction to the data sheet should be set to 0

And not to 1.

 

Is this a known bug in the chip?

Only bay setting DMODE to zero we got the Dtap to work correctly.

The PLL locks after 1 milisec.

If we set it to one we get Dtap that stop toggling after several hundred milliseconds.

We have test it on two boards, they both worked in the same.

Never did we get a One shot  Dtap.

 

Did you published a errata page to the drs4?

 

 

Thanks, Mony

 

mony orbach wrote:

Hi Stefan

Thanks for your input.

We are in the process of assemble another PCB board.

so soon we can compere between two boards.

As for the PLLEN bit, we set it.

We checked several times the soldering of the DRS4 using a microscope.

Everything looks ok.

In what method do you recommend to solder the DRS4?

 

Thanks for the invitation to meet.

120Km is not so far J

 

mony

Stefan Ritt wrote:

Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.

Stefan

mony orbach wrote:

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

    Reply  Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec 

surrey i forgot to update..

after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111

after making shore that a0-a3 never get 1111 value thae drs4 woks as expected.

The dtap toggols ok.

We can sample and read all the data channels.

So, putting A0-A3 value of 1111 even for very short period  " confuse " the DRS and then it start to behave in a strange manner.

 

mony

Stefan Ritt wrote:

While I can understand 1., I'm puzzeled by 2.

If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This is clearly stated in the data sheet.

Concerning the DMODE bit, we operate all (!) our chips with DMODE=1. Actually this is the default value. After a reset, all register bits are "1", which enables the PLL and causes DTAP to oscillate. If DMODE=1, the DTAP signal should toggle only once (!) since the domino loop is not closed. So the scope traces you showed previously are consistent with the standby mode, but not possible with ANY setting of DMODE.

Stefan

mony orbach wrote:

Hi

We have resolve the problem, the Dtap is now working correctly.

There were two problems:

  1. After configuration we put the all address bits to one (standby mode)

We are now setting the address bits to all zero. Failure

to do so result in Dtap  stop toggling after several hundred milliseconds.

  1. The DMODE bit in contradiction to the data sheet should be set to 0

And not to 1.

 

Is this a known bug in the chip?

Only bay setting DMODE to zero we got the Dtap to work correctly.

The PLL locks after 1 milisec.

If we set it to one we get Dtap that stop toggling after several hundred milliseconds.

We have test it on two boards, they both worked in the same.

Never did we get a One shot  Dtap.

 

Did you published a errata page to the drs4?

 

Thanks, Mony

 

 

Entry  Wed Feb 10 02:57:55 2010, pepe sanchez lopez, Hello 

hello i am an student and i want to do my final project with drs4 board and i really can´t find how to open waveform file and how can i save or opened many of them quickly.

if you can tell me how i will be very grateful.

thanks,

kind regards.

Entry  Wed Nov 30 17:48:39 2016, samridha kunwar, DRS4 Initiation 

I am having a general problem getting read back using the ROI mode.  In the transparent mode everything looks good. These are the steps that I take:

1) configure register (b"11111111",addr = "1100")

2) configure write shift register (b"11111111", addr = "1101")

3)  assert DENABLE and DWRITE

4) wait for trigger

5) on trigger deassert DWRITE

6) Strobe RSRLOAD

7)Set drs4 address to enable all channels (address = "1001")

8)give n SRCLK pulses

9) goto 3 and repeat.

 

Am I missing something? Everything looks straight forward based on the manual yet in the readout mode I only get noise. I do get the stop position on SROUT and the refclk is at 475 KHz as desired and I get the desired behaviour  for DTAP toggling at the same frequency as refclk.

    Reply  Fri Dec 2 15:32:52 2016, samridha kunwar, DRS4 Initiation 

Thanks for replying Stefan.

I was more so just concerned with the steps in the firmware when I had asked. However, yes the ROFS (1.05V) and O-OFS (0.9 V was 1.3 V earlier but, changed this becasue of ADC input requirements) are per spec, the VDD voltages are all there and input voltages are within the rails and finally the RSLOAD  (16 ns) too is ok. Looking at your eval board firmware , on appearance it looks exactly like what I am doing. I thought maybe I was/ still am missing some intermediate addressing stage. What I wrote earlier is what I still have.

Stefan Ritt wrote:

Uhh, there are 1000 things which might be wrong. A bit like "my car is not working, it makes strange noise". Without having a look under the hood, there is just some wild guessing:

- Is your ROFS input at the right value? Your O-OFS?

- All VDD voltages there? Input voltage outside the rails?

- Your RSLOAD pulse long enough (>10ns)

- What happens if you put a really big sinal at the input, like 100 MHz sine wave with 2V p-p

The easiest is to have a look at the evaluation board and copy your new board like 1:1, also copy the VHDL readout code. Much easier that to start from scratch.

Stefan

 

 

samridha kunwar wrote:

I am having a general problem getting read back using the ROI mode.  In the transparent mode everything looks good. These are the steps that I take:

1) configure register (b"11111111",addr = "1100")

2) configure write shift register (b"11111111", addr = "1101")

3)  assert DENABLE and DWRITE

4) wait for trigger

5) on trigger deassert DWRITE

6) Strobe RSRLOAD

7)Set drs4 address to enable all channels (address = "1001")

8)give n SRCLK pulses

9) goto 3 and repeat.

 

Am I missing something? Everything looks straight forward based on the manual yet in the readout mode I only get noise. I do get the stop position on SROUT and the refclk is at 475 KHz as desired and I get the desired behaviour  for DTAP toggling at the same frequency as refclk.

 

 

Entry  Wed Feb 22 11:36:51 2012, sonal, DRS4- analog pulse counting 

Hello Sir,

Regarding to analog pulse counting by using DRS4 Rev.2.0 board, you have said that "There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months."

I am interested in it. I have DRS4 Rev.2.0 board. I have FPGA and Microcontroller firmware for this board. How can I implement this concept of counting pulses?

 


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