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Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?        Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register?        Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?    Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem         Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem         Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem     Tue Nov 26 15:36:39 2013, Dmitry Hits, reducing sampling speed        Tue Nov 26 15:38:13 2013, Stefan Ritt, reducing sampling speed    Tue May 4 21:18:28 2021, Abaz Kryemadhi, recording only timestamp and amplitude and/or filesize maximum        Wed May 5 10:12:44 2021, Stefan Ritt, recording only timestamp and amplitude and/or filesize maximum    Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ??        Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??    Sun Jun 12 08:45:52 2016, Michael, problems of DRS4    Sun Jun 12 08:49:54 2016, Michael, problems of DRS4        Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4    Thu Jan 25 05:24:05 2018, chen wenjun, problem with the drscl(drs507)        Thu Jan 25 08:00:16 2018, Stefan Ritt, problem with the drscl(drs507)        Thu Jan 25 08:07:32 2018, chen wenjun, problem with the drscl(drs507)    Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4        Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4

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