| ID |
Date |
Author |
Subject |
Text |
 |
|
95
|
Tue Jun 22 11:02:30 2010 |
Stefan Ritt | Reset of DRS4 |
|
|
|
97
|
Tue Jun 22 11:35:18 2010 |
Stefan Ritt | Reset of DRS4 |
|
|
|
99
|
Mon Jul 12 16:07:37 2010 |
Stefan Ritt | Announcement evaluation board V3 | Dear DRS4 users,
a new version of the evaluation board
has been designed and is in production now. |
|
|
105
|
Mon Jul 19 12:47:17 2010 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
|
107
|
Wed Jul 21 10:58:20 2010 |
Stefan Ritt | ENOB of DRS |
|
|
|
111
|
Tue Nov 16 16:38:06 2010 |
Stefan Ritt | Reference design for DRS4 active input buffer |
|
|
|
113
|
Sat Feb 19 22:46:35 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
|
114
|
Mon Feb 21 08:10:31 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
|
116
|
Fri Feb 25 10:13:51 2011 |
Stefan Ritt | Announcement digital pulse processing workshop | Dear colleague,
if you live not so far from Zurich,
you might be interested in this workshop: |
|
|
118
|
Fri Apr 15 08:28:54 2011 |
Stefan Ritt | Fixes to DOScreen.cpp for recent built on linux | > Hello,
>
> I was just building version 3.1.0 and ran |
|
|
120
|
Thu Jun 2 21:01:29 2011 |
Stefan Ritt | Removing spikes |
|
|
|
122
|
Tue Jul 5 10:09:43 2011 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
|
124
|
Wed Jul 13 04:26:52 2011 |
Stefan Ritt | Fixed Patter Timing Jitter |
|
|
|
126
|
Wed Sep 7 16:56:43 2011 |
Stefan Ritt | DRS4 and AD9222 |
|
|
|
129
|
Fri Sep 9 09:31:33 2011 |
Stefan Ritt | DRS4 and AD9222 |
|
|
|
131
|
Mon Sep 19 08:53:22 2011 |
Stefan Ritt | compilation error for version 4.0.0 on linux |
|
|
|
133
|
Sat Oct 22 00:40:02 2011 |
Stefan Ritt | DRS4 eval board: readout rate |
|
|
|
135
|
Mon Oct 24 10:30:15 2011 |
Stefan Ritt | Phase Shift for ADC Readout |
|
|
|
137
|
Tue Nov 1 11:07:02 2011 |
Stefan Ritt | How to link PMT |
|
|
|
139
|
Mon Dec 12 16:43:04 2011 |
Stefan Ritt | DC coupled DRS4 input stage | In the attachement you will find a working
DC-coupled input stage to the DRS4 chip.
The bandwidth of this design is about 700 |
|