| ID |
Date |
Author |
Subject |
Text |
 |
|
392
|
Sun Oct 19 14:36:54 2014 |
Chris Tully | coverting the xml file format into binary | Hi,
Is there a straightforward
way to convert the xml file format into the |
|
|
671
|
Wed Mar 14 09:13:39 2018 |
chen wenjun | confusion about the description in drs.cpp | Hi,Stefan:
recently,whtn I study the
drs.cpp code ,I found that the buffer[1] |
|
|
673
|
Fri Mar 16 14:00:06 2018 |
Stefan Ritt | confusion about the description in drs.cpp | The FPGA is very small, so it only has
an address space of 256 bytes. Look at the
definition in DRS.cpp |
|
|
689
|
Sun May 6 08:13:37 2018 |
chen wenjun | confusion about the description in drs.cpp | Hi Stefan:
I'm still confused that
althought the 8 bits buffer is enough,the |
|
|
690
|
Sun May 6 11:45:09 2018 |
Stefan Ritt | confusion about the description in drs.cpp | The locbus_addr is indeed 32 bits wide,
since the firmware was originally derived
from some firmware running in a VME crate, |
|
|
130
|
Fri Sep 16 22:06:07 2011 |
Andriy Zatserklyaniy | compilation error for version 4.0.0 on linux | Hi Stefan,
When I compiled DRS4 software version
4.0.0 on Linux (Debian Squeeze) I got this |
|
|
131
|
Mon Sep 19 08:53:22 2011 |
Stefan Ritt | compilation error for version 4.0.0 on linux |
|
|
|
371
|
Fri Sep 12 14:57:22 2014 |
Dmitry Hits | compilation error for v5.0.2 | Hi,
I am getting the following compilation
error when trying to compile version 5.0.2 |
|
|
372
|
Fri Sep 12 16:08:49 2014 |
Stefan Ritt | compilation error for v5.0.2 |
|
|
|
373
|
Fri Sep 12 16:38:24 2014 |
Dmitry Hits | compilation error for v5.0.2 |
|
|
|
375
|
Mon Sep 22 14:52:21 2014 |
Stefan Ritt | compilation error for v5.0.2 |
|
|
|
237
|
Thu Apr 11 22:41:13 2013 |
Bill Ashmanskas | code/details for optimal DRS4 timing calibration? | Hi Stefan,
Is either some example code or a
detailed written description available for |
|
|
240
|
Fri Apr 12 08:38:17 2013 |
Stefan Ritt | code/details for optimal DRS4 timing calibration? |
|
|
|
223
|
Thu Feb 28 10:47:14 2013 |
Dmitry Hits | clock and trigger outs | Hi,
I am considering using the DRS4 evaluation
board as an ADC card for the wire chamber |
|
|
224
|
Thu Feb 28 12:58:44 2013 |
Stefan Ritt | clock and trigger outs | > Hi,
> I am considering using the DRS4 evaluation
board as an ADC card for the wire chamber |
|
|
358
|
Mon Jul 14 19:03:05 2014 |
Yves Bianga | change cascading from 1024 to 2048 bins for each input channel | Hello,
I want to ask
whether it is possible to modify a Evaluation |
|
|
359
|
Wed Jul 16 12:10:19 2014 |
Stefan Ritt | change cascading from 1024 to 2048 bins for each input channel |
|
|
|
229
|
Tue Mar 26 01:17:59 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
All I'm trying to do is cascade one
input signal, though all available channels, |
|
|
231
|
Thu Apr 4 11:32:21 2013 |
Stefan Ritt | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
|
|
232
|
Fri Apr 5 02:21:33 2013 |
Jill Russek | cascading -- DRS4 Osci.cpp & DRS.cpp |
|
|