DRS4 Forum
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Entry  Tue Mar 28 21:53:12 2017, Jim Freeman, drscl doesn't find eval board but drsosc does (Windows 7) 
Entry  Fri Oct 16 09:51:03 2009, Jinhong Wang, DSR4 Full Readout Mode 
Entry  Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4 
Entry  Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4 
Entry  Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4 QFN_package.jpg
Entry  Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4 
    Reply  Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4 
    Reply  Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4 
    Reply  Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model 
    Reply  Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4 
    Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 
Entry  Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4 
    Reply  Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4 
    Reply  Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4 
Entry  Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter 
Entry  Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS 
    Reply  Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer 
    Reply  Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter hist_stoppos.jpg
    Reply  Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter 131MHz.jpg
Entry  Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors 
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