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ID Date Authorup Subject
  742   Thu Feb 21 09:51:24 2019 Lev Pavlovno board found

Hey. Yes, the program is running as administrator. By the way, this is win10. Your drs_exam works fine. My drs_exam compiled wrote no board found. Maybe this is a problem like in the post https://elog.psi.ch/elogs/DRS4+Forum/698. Maybe there were solutions to the problems?

Thank You

Lev

Stefan Ritt wrote:

No idea. Maye some access problem. Have you tried to start your program under an admin account?

Stefan

Lev Pavlov wrote:

Great, drs_exam compiles without problems. Now when you run the compiled file drs_exam writes board not found, but drsosc and drscl work without problems. What could possibly be the matter?

thanks for your patience

Lev

Stefan Ritt wrote:

You have to change the path to libusb-1.0.lib to the one where you installed it.

Stefan

Lev Pavlov wrote:

Hey. Strange problem. Why does the compiler refer there at all? Library installed drsosc works

 

LINK : fatal error LNK1104: cannot open file "C:\meg\online\drivers\drs\libusb-1.0\libusb-1.0.lib"

 

 

 

 

  744   Mon Feb 25 08:40:44 2019 Lev Pavlovno board found

 

Hello. When compiling drs_exam, do you need to use a "static "version of usblib or a "dynamic" version?"The problem with "no board found" is not solved. Thanks for your help.

Lev.

Stefan Ritt wrote:

Could be. Have you tried that elog:657

Stefan

Lev Pavlov wrote:

Hey. Yes, the program is running as administrator. By the way, this is win10. Your drs_exam works fine. My drs_exam compiled wrote no board found. Maybe this is a problem like in the post https://elog.psi.ch/elogs/DRS4+Forum/698. Maybe there were solutions to the problems?

Thank You

Lev

Stefan Ritt wrote:

No idea. Maye some access problem. Have you tried to start your program under an admin account?

Stefan

Lev Pavlov wrote:

Great, drs_exam compiles without problems. Now when you run the compiled file drs_exam writes board not found, but drsosc and drscl work without problems. What could possibly be the matter?

thanks for your patience

Lev

Stefan Ritt wrote:

You have to change the path to libusb-1.0.lib to the one where you installed it.

Stefan

Lev Pavlov wrote:

Hey. Strange problem. Why does the compiler refer there at all? Library installed drsosc works

 

LINK : fatal error LNK1104: cannot open file "C:\meg\online\drivers\drs\libusb-1.0\libusb-1.0.lib"

 

 

 

 

 

 

  749   Fri Apr 12 09:39:30 2019 Lev Pavlovmulti-board

Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks
  751   Fri Apr 12 09:59:15 2019 Lev Pavlovmulti-board

 

I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but simultaneously in parallel to all the boards, will this shift go? Thanks

Lev Pavlov

Stefan Ritt wrote:

Subtract 16 ns from your measured value ;-)

Stefan

Lev Pavlov wrote:

Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks

 

 

  342   Tue May 13 19:34:58 2014 Luka Pavelicdrsosc binary to cern ROOT file conversion

Hi,

Does anybody have program for conversion from binary or xml to cern ROOT *.root file?
 

Thank you for any help you can provide,
Luka Pavelic


 

  344   Tue May 13 22:03:47 2014 Luka Pavelicdrsosc binary to cern ROOT file conversion

Thank you for your fast and very helpful replay.

I made it work with drsosc version 4 but with version 5 i am getting weird results. Is it possible that they changed binary formatting?

 

  853   Thu Dec 23 03:42:26 2021 LynseyDRS4 request assistance

Dear Sir or Madam,

      Good morning,I am using drs4 chip, and the measured fDTAP == 1/350ns, that is, fDOMINO == 1 / 350ns * 2048 == 5.8GHz.

     I have three questions:

                              1. Is fDOMINO determined by the chip itself?

                              2. C1, C2 and R2 are TBD. I don't know how many to choose. Is there an algorithm?

                              3."Configure Write Shift Register to contain all 1's",What, pray, is the meaning of “1's"?

                                                                                                                                                          Truely yours.

 

  854   Fri Dec 24 03:13:32 2021 LynseyTrouble getting PLL to lock

I also design the circuit myself. Our problem is the same. Can we communicate?

Stefan Ritt wrote:

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

 

  882   Tue Apr 12 10:40:36 2022 LynseyShun 

Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding waveforms.

In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time?

thank you very much

  884   Thu Jun 16 05:31:25 2022 LynseyShun 

Thank you very much for your help!

Stefan Ritt wrote:

A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works in our designs. Maybe double check the address lines with an oscilloscope.

Stefan

LynseyShun wrote:

Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding waveforms.

In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time?

thank you very much

 

 

  885   Fri Jun 24 09:57:36 2022 LynseyShunSpikes/noise sensitive to clock settings?

Hello, I now have periodic spikes in CH0 and CH1 output. How can I eliminate these spikes? I'm sorry I didn't understand your elimination method. Please explain the method in detail. Thank you very much

Stefan Ritt wrote:

elog:824

Sean Quinn wrote:

Dear DRS4 team,

I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy data (post-calibration) with periodic spikes.

In the below plot

  • CH0 & CH1 are muon pulses from a scintillator + SiPM detector
  • CH8 is a 25 MHz sinewave (in phase with all generated board clocks)
  • Transparent mode = ON
  • ROI = OFF, "full readout mode", first sample = cell 0
  • DRS REFCLK = 1 MHz (2 GS/s)
  • ADC & SR CLK = 16 MHz, 0 deg. offset

 

After I modify some clock settings, things seem to improve dramatically, and the spike behavior changes

  • ADC and SR CLK = 15 MHz, 0 deg. offset
  • Transparent mode = ON
  • ROI = ON (just for testing purposes)
  • Add 1.064 ns skew to DRS REF CLK
  • NOTE: Unfortunately due to a design mishap, the ADC and FPGA clock use a phase-locked output pair on our clock synthesis chip, so we cannot fine-tune the skew for it.

Observed differences

  • Spike polarity seems inverted
  • Spikes limited to smaller number of cells now?
  • Spike amplitude reduced
  • Overall baseline variance seems better
  • New large positive spike artifact on CH0 that seems inverted on CH1
  • CH8 seems unaffected by large spikes?

Artifacts seem related to clock configuration, but I am sort of in the dark on what might be happening from a first-principles point of view. Any tips?

 

Warm regards,

Sean

 

 

  521   Wed May 11 04:01:14 2016 MaksatDRS4 Macro to save events

Dear Stefan,

I am trying to setup DRS inside radiation enclosure and would like to write a simple script that will automatically save certain number of events.

Could you please point to me an example that can I use for Mac OS? I saw there is drs_exam.cpp in the directory but was not able to get work in Mac OS. Any help would be greatly appreciated.

Thanks

 

 

  119   Wed Jun 1 09:57:43 2011 Martin PetriskaRemoving spikes

I have DSR4 eval board. Found that there are spikes in channels. Procedure Osc::RemoveSpikes to remove them looks litlle dificult. There is simple way, if you doesnt need to measure all 4 channels.Spikes are in all channels, and it looks like they are same in time and value between channels. To remove them, if you are not using one channel, substract that unused channel with spikes from used channel and your data will be without spikes. If you need all 4 inputs, then may be channel 9 could be substracted.

  158   Tue Mar 20 16:23:33 2012 Martin Petriskatriger for measuring time between pulses in channels

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

  160   Wed Mar 21 09:33:00 2012 Martin Petriskatriger for measuring time between pulses in channels

Stefan Ritt wrote:

Martin Petriska wrote:

 I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data. 

Ok, except this, I would have a question regarding to the new trigering posibility in V4 board. At this time, I am using Ztec ZT4612 which has some pattern triger posibility. Output from this card is used as an external trigger. Regarding this I have found a problem. Pulses from PMT have about 5-8 ns width. But I need to measure time diferences between pulses in range from 0-50ns. Problem is, that coincidence between pulses is working only on short pulse area (5-8ns) when they are overlapped. Additionaly the result histogram of time diferences is proportional to the pulse shapes. I solve this problem enabling 20MHz LPF filter in ZT4612, so the pulses are wider and overlaped on larger area. But, how it is with the V4 board? Will it trigger if I have for example one 5ns pulse on begiinning of CH1 and second pulse for example 50 ns later on Ch2 with the same probability when pulses are in the same time position?

  185   Mon Oct 29 18:30:28 2012 Martin PetriskaGetWave

 I have some question according to GetWave function. In drs_exam.cpp simple GetWave(0,0,wave_array[]) etc...is used. Is there primary (cell) calibration, secondary calibration (Readout) and remove Spikes used, as in DRS Oscilloscope application?

  204   Thu Dec 6 09:23:36 2012 Martin PetriskaEVM rev4 board trigger change and drs_example

 I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in drs_exam.cpp for example triggering on Ch0 && CH1 ?

Software 4.0.0, windows version.

Here is old trigger initialisation: 

b->EnableTrigger(0,1);

b->SetTriggerSource(0);

b->SetTriggerLevel(0.25, false);

b->SetTriggerDelayNs(0);

 

Btw. Is it possible to set up different trigger Levels for each channel ?

 

(If there is some interest here is my code in Qt, still aplha) http://sourceforge.net/p/qtpals/code

  217   Wed Feb 13 16:58:40 2013 Martin PetriskaNonuniform sampling

 Are there any plans to include reconstruction of nonuniform sampling  in DRS4 to get uniformly sampled data?

Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel

and plan to implement it, but may be somebody has it done before me.

 

  248   Tue May 21 13:32:13 2013 Martin Petriskamac osx 10.6
> Hi,
> 
> I would like to use the DRS4 with my macbook pro running osx 10.6.8.
> I have installed the wxWidgets and the libusb-1.0 libraries and I am using the Linux code vers. 4.0.1. After
> compilation, the following errors come out:
> 
> ld: warning: in musbstd.o, file was built for unsupported file format which is not the architecture being linked
> (i386)
> ld: warning: in mxml.o, file was built for unsupported file format which is not the architecture being linked (i386)
> ....
> ....
> ld: warning: in main.o, file was built for unsupported file format which is not the architecture being linked (i386)
> Undefined symbols:
>   "_main", referenced from:
>       start in crt1.10.6.o
> ld: symbol(s) not found
> collect2: ld returned 1 exit status
> make: *** [drsosc] Error 1
> 
> 
> Do you have any idea on how to solve the problem ?? or maybe do you have a package working with osx 10.6 ? I
> remember to have seen, long time ago, a package that could work with 10.6 (or 10.5 ?), but I cannot find it now
> (but maybe I remember wrong).
> 
> Thanks for any help,
> 
> Enrico

it looks like 64bit vs 32bit problem, you have to compile all libraries for the same architecture. Maybe, make clean to 
remove all precompiled object files .o and recompile it again. Try to compile first that simple example without wxWidgets.

Martin
  321   Thu Jan 9 10:58:19 2014 Martin Petriskav5 software with v4 board calibration

 Hi

Question:

In v4 board, which channel has best calibration ?

Should it be possible to simulate v5 board and read calibration values for v4 board by other method .. for example using external calibration signal source connected to all channels? 

Is it  needed to detach all input signals from EVM board during calibration ?( I see there are switches on channel inputs.)

Some comments: averager.h, averager.cpp are missing in windows v.5 sources (it should be copied from linux sources)

 

PF2014 and thank You for development new EVM 5 and new time precision.

 

Martin

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