 Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
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Thank you very much for the answer, I really appreciate your help.
Thanks!
Gerard |
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Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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In meantime I even updated the manual.
Stefan
Gerard |
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Mon Dec 23 19:31:31 2024, Matias Henriquez, Trigger OUT pulse width variable from 100 us up to 100 ms
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Given this new scenario, what is the maximum rate of events that can be processed then (a rough estimation would be great, 1/2ms?)? is it mainly limited
by the USB data transmission and the PC? How does the logic of the trigger and DRS4 data sampling works inside the FPGA in general terms? e.g: trigger
activated -> dwrite ON -> ADC acquisition -> busy until data has been shipped off to the PC -> free to process new events. |
 Thu Jul 18 01:03:44 2019, Ismael Garcia, Trace Impedance 
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Hi Steffan,
I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on |
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Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance
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The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms
and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not
exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. |
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Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance
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When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508)
buffer
and the inputs of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8? |
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Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance
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The DRS4 input is high impedance. So if you like you can terminate it with 100 Ohm differentially and route it with 100 Ohm. But if you keep the lines
short, the reflection is negligible. That’s what we made on the evaluation board.
Ismael |
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Wed Oct 21 15:03:13 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
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Dear Stefan,
I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register. |
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Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register
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Dear Seiya,
1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11:
SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. |
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Tue Oct 27 15:02:09 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
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Dear Stefan,
Thank you for your reply. |
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Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register
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This is a static shift register, so you can make the clock as slow as you want. Actually I don't use a "clock", I just use a data pin I
control via a state machine in the VHDL code. This way I have more control over the edges. I need several (internal) clock cycles to produce one SRCLK
clock cycle, but that does not matter for the DRS. |
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Wed Oct 28 04:32:19 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register
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Dear Stefan,
OK, it's good to hear! Thank you! |
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Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
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Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
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Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
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That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
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Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
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Thanks a lot for the quick response.
We will do as you suggest.
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Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail
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Hi,
has anyone experienced a shutdown of the DRSosc.exe or DRScl.exe when executing a Timing Calibration? Also, when we add the command b->CalibrateTiming(NULL);
to the drs_exam.cpp and run the exe, our program shuts down immediately and windows shows an error message (identical to DRSosc and DRScl). |
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Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail
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Hannes Wachter wrote:
Hi, |
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Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform
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Hi DRS4 Experts,
I have been analyzing DRS4 binary data with scripts based on Stefan's (very helpful!) macro:
https://midas.psi.ch/elogs/DRS4+Forum/361 |
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Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform
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In the mentioned read_binary.cpp file you have the line where you read the event header
i = fread(&eh, sizeof(eh), 1, f);
The C structure eh now contains the full timestamp, and you can access it with |
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Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards
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Hello,
I 'm using four evaluation boards v.3 to construct the multi-board DAQ system. One channel for each board is used as reference clock, then
calibrate timing offline, which allow below 10ps resolution between boards. |