 Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock
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Which serial number has the board? Has it been in use before or is it a new board?
Stefan
Alexey |
Thu Nov 24 13:24:26 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data 
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The code in the macro is correct. The misconception lies in the definition what "sample 0" means. Please view the attached picture. This is
simplified case with a DRS chip with only 8 cells (instead of 1024). There are two events (blue and red). In the first event, the chip is stopped at trigger
cell (tc) 2, in the second case at 5. Since the readout starts with the trigger cell, the first readout sample in the first event belongs to cell #2, the |
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Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock
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Have you tried to unplug and re-plug the board a few times? According to our database, you should have three boards. Do all three show the same behavior
or only this board? In case all three show this, it could be a hint of a software problem. If two boards are good and one is bad, this would be a hint
of a hardware problem (broken board). |
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Wed Nov 30 08:53:58 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The inverter chain in the DRS4 is continously running in a ring. Once you get a trigger, it is stopped. This happens in any of the 1024 cells. The last
cell which sampled a signal plus ne is called "trigger cell". In the previous diagram in event #1, the last cell sampling was "1",
so the trigger cell is "2". In event 2 (red case), the trigger cell is 5. If you would run like this, you see only the part of the waveform BEFORE |
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Wed Nov 30 10:45:29 2016, Stefan Ritt, Long timing between two channels
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You cannot measure times longer than 1024/sampling rate.
Stefan
Randall |
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Wed Nov 30 19:05:24 2016, Stefan Ritt, DRS4 Initiation
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Uhh, there are 1000 things which might be wrong. A bit like "my car is not working, it makes strange noise". Without having a look under the
hood, there is just some wild guessing:
- Is your ROFS input at the right value? Your O-OFS? |
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Fri Dec 2 16:47:37 2016, Stefan Ritt, DRS4 Initiation
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No, I can't think of anything else. There is no intermediate addressing stage. The only thing which sometimes happens is that the QFN76 package is
not soldered correctly. If you don't have this under control, some pins might have a bad contact. You can check this by touching with a oscilloscope
probe not the PCB pads but really the pins from the side, which is a bit tricky. |
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Fri Jan 13 13:16:09 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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The error probably comes from the fact that the drsosc.exe application is a 64-bit application and cannot be executed under XP any more. Unfortunately
XP is forbidden at our institute for security reasons, so I have no machine around where I could compile the executable fro XP. Another problem is the
libusb library used by drsosc.exe. Not sure if there is a XP version available any more. Have a look yourself at http://www.libusb.org/wiki/windows_backend |
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Fri Jan 13 13:50:10 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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Can you try that executable under XP: https://www.dropbox.com/s/j1n09afhbmh0zzu/drsosc.exe?dl=0
Gregor
Kramberger wrote:
Hi all |
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Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems
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In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than
4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in
the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if |
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Tue Jan 31 08:40:04 2017, Stefan Ritt, LLD and ULD discriminations,
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Not inside the board. Each channel has a single discriminator. You can select to trigger on a rising or falling edge, but you don't have two levels.
What you can do however is to make an external trigger, like using old NIM logic. You can make discrimaiton with different levels and use a coincidence
unit to combine them. Then feed the trigger into the external trigger input of the evaluation board (5V TTL level, not NIM level!). |
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Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl
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This is indeed currently not implemented. But there is a simple C program drs_exam.cpp, which connects to a board and safes some data. You could modify
that program to your needs.
Stefan |
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Wed Apr 5 12:28:28 2017, Stefan Ritt, drscl doesn't find eval board but drsosc does (Windows 7)
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Two people report now this problem, while this works fine at our lab. So I'm puzzled right now.
I attach two screenshots from the device manager and the Command Line interface. Can you compare it with what you see? Which is the firmware
version of your evaluaiton board? |
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Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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You have to download the package for your board, which then includes also the correct firmware for your board. If you have a V4 board, your firmware
is in drs-4.0.2.tar.gz which you can download from Dropbox at https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Martin |
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Mon Apr 10 10:50:57 2017, Stefan Ritt, drs4 registers behaviour
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Using the RESET line to reset registers is not a good idea since it can have some bad side-effects. The READ SHIFT register is NOT affected by RESET,
so you have to inititialize these registers differently. To set a "1"-value at a defined position, you have to follow figure 11 in the data sheet.
Once you executed that, your "1" is always at the same posiiton (namely cell #0), so after 1024 clock cycles you arrive at the same state, and |
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Mon Apr 10 14:05:17 2017, Stefan Ritt, drs4 registers behaviour
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1. WRITE SHIFT register and CONFIG registers are initialized to "1" on power up, but if you want to change that, use A0-A3 etc. as you indicated.
2. If you address the READ SHIFT register by applyin "1011" to A0-A3, the input of the register is connected to SRIN. So in fig. 11,
you apply 1023x"0" plus 1x"1", which effectively clears the register and keeps one "1" at the last position, so on the next |
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Tue Apr 11 09:41:44 2017, Stefan Ritt, drs4 registers behaviour
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What I do is the following: Have the RESET input unconnected. When you power up, this makes an internal reset during the power up, and that's all
you need. Then configure your registers using the sequences described in the manual. Then do not touch the RESET any more.
Stefan |
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Thu Apr 13 16:50:18 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Hard to say. Timing calibration is quite delicate. If you start from scratch, better read this paper: https://arxiv.org/abs/1405.4975
If you try to extract the code from DRS.cpp, better read the paper, too. Probably it will not be possible to develop or extract the code without
knowing how it works. |
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Thu Apr 13 17:02:01 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Than you can try to isolate the code. Note that different SCAs might work differently. Like the DRS4 has a channel-to-channel jitter which others might
not. But you will see.
Stefan |
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Wed Apr 19 12:17:25 2017, Stefan Ritt, Wave rotation during transfer from the board?
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This is correct. Actually the amplitude array is rotated already inside the DRS4 chip. So the readout starts with the stop cell plus one. If you do not
do anything, the waveform is already "rotated". If you want the waveform to start with physical cell #0, you have to "unrotate" it.
Stefan |