| ID |
Date |
Author |
Subject |
Text |
 |
|
435
|
Thu Jul 2 08:53:17 2015 |
Felix Bachmair | Issue with Trigger rates below ~100Hz | Hi,
We did a further investigation
of this problem: |
|
|
434
|
Fri Jun 19 12:32:10 2015 |
Gregor Kramberger | drs 5.03 and windows 8.1 |
|
|
|
433
|
Thu Jun 18 17:33:05 2015 |
Gregor Kramberger | drs 5.03 and windows 8.1 | I have problems with driver installation
on windows 8.1 (software version 5.03).
I have sen that that has been an issue before |
|
|
432
|
Tue Jun 16 22:26:41 2015 |
Stefan Ritt | DRS4 Evaluation Board Osc Application | There is a horizontal position slider in
the "Horizontal" box on the right
side below the trigger delay. Use it. |
|
|
431
|
Tue Jun 16 20:45:54 2015 |
Michael Buadelk | DRS4 Evaluation Board Osc Application | Hi, I have a DRS4 v5 evaluation board and
I have a novice question about the oscilliscop
application. When I connect it to a photo-detector |
|
|
430
|
Fri Jun 5 13:32:03 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | Actually we should take this offline not to
pester other DRS users which are not interested
in this topic. Please call me directly (3728) |
|
|
429
|
Fri Jun 5 13:29:55 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | Do the following:
Use the TRG OUT of the evaluation board as |
|
|
428
|
Fri Jun 5 13:15:35 2015 |
Felix Bachmair | DRS4 firmware UCF constraints | Hi Stefan,
No we only use one evaluation board. We use
the evaluation board as a part of our beam |
|
|
427
|
Fri Jun 5 12:07:38 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | I presume you have several evaluation boards
and want to run them in sync, right?
|
|
|
426
|
Wed Jun 3 09:07:38 2015 |
Stefan Ritt | Peculiar behavior of time values for Rev5 DRS4 EB | First of all, you should not use new boards
with old software. I try to keep the current
software compatible with old boards, but |
|
|
425
|
Tue May 26 11:27:27 2015 |
Felix Bachmair | DRS4 firmware UCF constraints | > > Hello, I'm using two DRS4 rev.5 boards
for 8ch readout and triggering.
> >
|
|
|
424
|
Sun May 24 09:34:27 2015 |
Peter Steinberg | Peculiar behavior of time values for Rev5 DRS4 EB | Hi -
I am setting up a new DRS4 rev5
but using drivers and software we were recently |
|
|
423
|
Sat May 23 11:03:20 2015 |
Felix Bachmair | Issue with Trigger rates below ~100Hz | Hi
We are working with the DRS 4 V5
version and we investigated an issue with |
|
|
422
|
Fri May 22 14:25:45 2015 |
Stefan Ritt | DRS4 firmware UCF constraints | > Hello, I'm using two DRS4 rev.5 boards for
8ch readout and triggering.
>
|
|
|
421
|
Tue May 19 14:14:45 2015 |
Ilja Bekman | DRS4 firmware UCF constraints | Hello, I'm using two DRS4 rev.5 boards for
8ch readout and triggering.
|
|
|
420
|
Wed May 13 16:25:24 2015 |
Stefan Ritt | transparent-mode voltage | To get the good linearity, you need indeed
ROFS = 1.05V. With a O-OFS of 0.9V, a zero
input signal would give you DRS_OUT+=1.05V |
|
|
419
|
Wed May 13 16:13:07 2015 |
Chenfei Yang | transparent-mode voltage | If using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate? |
|
|
418
|
Wed May 13 12:52:22 2015 |
Chenfei Yang | transparent-mode voltage | Yes. I use exactly the same scheme as you
mentioned. I'll try your solution.
|
|
|
417
|
Wed May 13 12:34:49 2015 |
Stefan Ritt | transparent-mode voltage | There might be a solution. How do you bias
th input of the
DRS4 chip? If you use a scheme as described |
|
|
416
|
Wed May 13 10:27:43 2015 |
Chenfei Yang | transparent-mode voltage | I'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you |
|