| ID |
Date |
Author |
Subject |
Text |
 |
|
31
|
Sun Jan 31 23:52:15 2010 |
Hao Huan | Failure In Flashing Xilinx PROM | Hi Stefan,
I have an old-version
DRS4 evaluation board which doesn't have |
|
|
32
|
Mon Feb 1 08:30:42 2010 |
Stefan Ritt | Failure In Flashing Xilinx PROM |
|
|
|
797
|
Tue Sep 22 17:45:26 2020 |
Elmer Grundeman | External triggering | Dear all,
I had a question about timing jitter
and external triggering. |
|
|
798
|
Wed Oct 7 10:56:03 2020 |
Stefan Ritt | External triggering | The trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise |
|
|
799
|
Wed Oct 7 11:17:52 2020 |
Elmer Grundeman | External triggering | I will try that, thanks!
|
|
|
645
|
Tue Dec 12 00:25:50 2017 |
Diego Yankelevich | External trigger using Raspberry Pi | Dear Steffan:
We have been able to use the
DRS4 using a Raspberry Pi but we have not |
|
|
646
|
Tue Dec 12 13:58:06 2017 |
Stefan Ritt | External trigger using Raspberry Pi | Indeed the code does not work for the current
evaluation board, it has been written for
a previous version and never been updated. |
|
|
843
|
Tue Oct 26 10:41:46 2021 |
Mehrpad Monajem | External trigger and drs_exam | Hi Stefan,
I have two problems regarding using |
|
|
844
|
Tue Oct 26 12:00:51 2021 |
Stefan Ritt | External trigger and drs_exam | 1. Why should your waveform start from
0 to 5ns? I don't get your point. Whenever
you trigger a readout, you get a 200ns wide |
|
|
846
|
Tue Oct 26 15:05:18 2021 |
Mehrpad Monajem | External trigger and drs_exam | Thanks for your reply.
1- I want to have a window size
of 25.6ns instead of 200ns at 5GSPS. I have |
|
|
2
|
Wed Jan 14 12:02:04 2009 |
Stefan Ritt | External Trigger Input requirements | Several people mentioned that the external
trigger input (TTL) does not work on the
DRS4 Evaluation Board Rev. 1.1. This is not |
|
|
3
|
Wed Jan 14 13:41:44 2009 |
Stefan Ritt | External Trigger Input requirements |
Another tricky issue comes from the
fact that the external TTL trigger and the |
|
|
629
|
Wed Sep 27 16:11:03 2017 |
Yoni Sher | Event acquisition pace for irregular timing | Hi,
I'm running a LIDAR application
that requires that every outgoing pulse be |
|
|
630
|
Mon Oct 2 16:08:05 2017 |
Stefan Ritt | Event acquisition pace for irregular timing | As written in the documentation, the DRS
evaluaiton board has a maximum trigger capability
of ~500 Hz. This is limited by the USB bus |
|
|
753
|
Thu Jun 20 01:36:48 2019 |
Andrew Peck | Evaluation firmware wait_vdd state | Dear Stefan,
I am working with others at UCLA
on a custom made board built around the DRS4. |
|
|
754
|
Fri Jun 21 12:54:47 2019 |
Stefan Ritt | Evaluation firmware wait_vdd state | Dear Andrew,
the posting you mention is still
accurate. Any power supply will drop when |
|
|
755
|
Mon Jun 24 23:07:35 2019 |
Andrew Peck | Evaluation firmware wait_vdd state | Dear Stefan,
Thanks so much for clarifying this.
We made wait_vdd a parameter controlled by |
|
|
153
|
Wed Feb 15 18:08:13 2012 |
Yuji Iwai | Evaluation Board v4 Trigger/Clock Connectors | Quick question - what type of connectors
are used for the trigger and clock in/out
on the v4 eval board? |
|
|
761
|
Sat Jul 13 01:00:15 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello,
I have recently obtained a DRS4
Evaluation Board (V5), but I am unable to |
|
|
762
|
Mon Jul 15 17:26:50 2019 |
Stefan Ritt | Evaluation Board Test Functionality | Have you set the trigger correctly to the
channel with your signal, polarity and level?
Do you undersand the difference between normal |
|