DRS4 Forum
  DRS4 Discussion Forum, Page 34 of 45  Not logged in ELOG logo
 Find |  Login |  Help 
 Full | Summary | Threaded | Show attachments  Show only new entries   889 Entries 
Goto page Previous  1, 2, 3 ... 33, 34, 35 ... 43, 44, 45   Next  
ID Date Author Subjectdown
  83   Tue May 18 08:23:07 2010 Stefan RittDVDD Problem of DRS 4

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Hi Stefan,

    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization of the Domino circuit doesn't help either. We tried different capacitors at DVDD and it seemed the larger the capacitance, the better the result--with a capacitor larger than 10nF some of the DRS chips could work happily in the normal way while if the capacitor is only 4.7nF all of them got very hot. Would you please provide some suggestions why there should be such a problem?

    Thanks a lot!

I found that sometimes even a reinitialization fails if the pull-down resistors are missing. So instead playing with capacitors at DVDD, I would just solder two resistors on the board which should fix the problem completely.

 Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

Something is wrong. I have 800 chips, and they all start up fine. Check with your scope the RESET, DSPEED, DENABLE and DTAP signals. When RESET is applied, DSPEED should go to 2.5 V. When DENABLE goes high, the domino wave is started and you should see DTAP toggle. DSPEED is then lowered by the PLL until DTAP matches your external reference clock. I usually keep DENABLE high all the time after initialization, so the domino wave just continues running.

Another problem could however be the chip readout. If some channel gives null output, it could be that your readout has a problem. Do you use RSRLOAD to initialize the readout sequence?

  85   Wed May 19 02:24:12 2010 Hao HuanDVDD Problem of DRS 4

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Hi Stefan,

    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization of the Domino circuit doesn't help either. We tried different capacitors at DVDD and it seemed the larger the capacitance, the better the result--with a capacitor larger than 10nF some of the DRS chips could work happily in the normal way while if the capacitor is only 4.7nF all of them got very hot. Would you please provide some suggestions why there should be such a problem?

    Thanks a lot!

I found that sometimes even a reinitialization fails if the pull-down resistors are missing. So instead playing with capacitors at DVDD, I would just solder two resistors on the board which should fix the problem completely.

 Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

Something is wrong. I have 800 chips, and they all start up fine. Check with your scope the RESET, DSPEED, DENABLE and DTAP signals. When RESET is applied, DSPEED should go to 2.5 V. When DENABLE goes high, the domino wave is started and you should see DTAP toggle. DSPEED is then lowered by the PLL until DTAP matches your external reference clock. I usually keep DENABLE high all the time after initialization, so the domino wave just continues running.

Another problem could however be the chip readout. If some channel gives null output, it could be that your readout has a problem. Do you use RSRLOAD to initialize the readout sequence?

 Yes; I used RSRLOAD to trigger readout of all channels in parallel so the asymmetry between channels of the same chip is really a big puzzle. Also during reset DSPEED indeed goes to 2.5V, but after reset the PLL will not try to lock with the external reference clock and lower DSPEED. Instead the Domino circuit just oscillates at the highest frequency by itself.

A more confusing discovery is that the SRIN level before starting the Domino wave could affect the behavior of the PLL. I mean the level of SRIN when the chip is at A="1111" or "1010". Is SRIN supposed to influence the chip even in these standby or transparent modes?

  86   Wed May 19 09:16:02 2010 Stefan RittDVDD Problem of DRS 4

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Hi Stefan,

    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization of the Domino circuit doesn't help either. We tried different capacitors at DVDD and it seemed the larger the capacitance, the better the result--with a capacitor larger than 10nF some of the DRS chips could work happily in the normal way while if the capacitor is only 4.7nF all of them got very hot. Would you please provide some suggestions why there should be such a problem?

    Thanks a lot!

I found that sometimes even a reinitialization fails if the pull-down resistors are missing. So instead playing with capacitors at DVDD, I would just solder two resistors on the board which should fix the problem completely.

 Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

Something is wrong. I have 800 chips, and they all start up fine. Check with your scope the RESET, DSPEED, DENABLE and DTAP signals. When RESET is applied, DSPEED should go to 2.5 V. When DENABLE goes high, the domino wave is started and you should see DTAP toggle. DSPEED is then lowered by the PLL until DTAP matches your external reference clock. I usually keep DENABLE high all the time after initialization, so the domino wave just continues running.

Another problem could however be the chip readout. If some channel gives null output, it could be that your readout has a problem. Do you use RSRLOAD to initialize the readout sequence?

 Yes; I used RSRLOAD to trigger readout of all channels in parallel so the asymmetry between channels of the same chip is really a big puzzle. Also during reset DSPEED indeed goes to 2.5V, but after reset the PLL will not try to lock with the external reference clock and lower DSPEED. Instead the Domino circuit just oscillates at the highest frequency by itself.

A more confusing discovery is that the SRIN level before starting the Domino wave could affect the behavior of the PLL. I mean the level of SRIN when the chip is at A="1111" or "1010". Is SRIN supposed to influence the chip even in these standby or transparent modes?

Just some ideas:

  • Is DENABLE really kept high all the time?
  • Is DRESET only applied once during initialization, after that it should stay high
  • Does  REFCLK+/REFCLK- really toggle at the required sampling speed / 2048?
  • Is the REFCLK really a good differential signal? Note that it must be biased properly since the DRS4 inputs are high impedance
  • Is the Bit1 in the Config Register really at "1" to enable the PLL?

The only way the SRIN level could affect the PLL is if you address the Config Register (A="1100") and you clock in a few bits with SRCLK.

Have you thought about 'crazy' things such as:

  • Defining the DRS4 chip wronly in your CAD software so that the pins are different from what you think?
  • Some soldering problem of the DRS4 chips (we had this in the past) so that some pins are not connected at all and others have shorts

I guess you checked most of the things, so I'm just wildly guessing in order to stimulate some thoughts.

The ultimate check would be to get one of the evaluation boards (I sent a few to Jean-Francois Genat some time ago...) and compare the DRS4 signals pin by pin.

  91   Fri Jun 18 11:31:20 2010 Jinhong WangDVDD Problem of DRS 4

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Hi Stefan,

    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization of the Domino circuit doesn't help either. We tried different capacitors at DVDD and it seemed the larger the capacitance, the better the result--with a capacitor larger than 10nF some of the DRS chips could work happily in the normal way while if the capacitor is only 4.7nF all of them got very hot. Would you please provide some suggestions why there should be such a problem?

    Thanks a lot!

I found that sometimes even a reinitialization fails if the pull-down resistors are missing. So instead playing with capacitors at DVDD, I would just solder two resistors on the board which should fix the problem completely.

 Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

Something is wrong. I have 800 chips, and they all start up fine. Check with your scope the RESET, DSPEED, DENABLE and DTAP signals. When RESET is applied, DSPEED should go to 2.5 V. When DENABLE goes high, the domino wave is started and you should see DTAP toggle. DSPEED is then lowered by the PLL until DTAP matches your external reference clock. I usually keep DENABLE high all the time after initialization, so the domino wave just continues running.

Another problem could however be the chip readout. If some channel gives null output, it could be that your readout has a problem. Do you use RSRLOAD to initialize the readout sequence?

 Yes; I used RSRLOAD to trigger readout of all channels in parallel so the asymmetry between channels of the same chip is really a big puzzle. Also during reset DSPEED indeed goes to 2.5V, but after reset the PLL will not try to lock with the external reference clock and lower DSPEED. Instead the Domino circuit just oscillates at the highest frequency by itself.

A more confusing discovery is that the SRIN level before starting the Domino wave could affect the behavior of the PLL. I mean the level of SRIN when the chip is at A="1111" or "1010". Is SRIN supposed to influence the chip even in these standby or transparent modes?

Just some ideas:

  • Is DENABLE really kept high all the time?
  • Is DRESET only applied once during initialization, after that it should stay high
  • Does  REFCLK+/REFCLK- really toggle at the required sampling speed / 2048?
  • Is the REFCLK really a good differential signal? Note that it must be biased properly since the DRS4 inputs are high impedance
  • Is the Bit1 in the Config Register really at "1" to enable the PLL?

The only way the SRIN level could affect the PLL is if you address the Config Register (A="1100") and you clock in a few bits with SRCLK.

Have you thought about 'crazy' things such as:

  • Defining the DRS4 chip wronly in your CAD software so that the pins are different from what you think?
  • Some soldering problem of the DRS4 chips (we had this in the past) so that some pins are not connected at all and others have shorts

I guess you checked most of the things, so I'm just wildly guessing in order to stimulate some thoughts.

The ultimate check would be to get one of the evaluation boards (I sent a few to Jean-Francois Genat some time ago...) and compare the DRS4 signals pin by pin.

 Hi Stefan

       I designed the evaluation board for our experiment. On our boards, I  encountered the similar problem when working on the PLL of DRS4. I compared the following two configuration process, which on with PLL locked, the other not,

   Process1: 

       step 1: Set DEnable and DWrite low, 

      Step2 : Reset DRS4 with a negative pulse of about 900 ns

      Step3: Set DEnable high,  thus do nothing but wait

       I found DRS4 PLL working and locked. 

  

  Process 2:

   Step 1: Set DEnable and DWrite low, 

  Step2 : Reset DRS4 with a negative pulse of about 900 ns 

  Step3: Set Config. Register( "11111111" .of course, this step was not necessary, just to see whether SPI was working properly from DTAP when set to "11111110")

  Step4: Set The read shift Register ( full read out mode)

  Step5: Set DEnable high, 

  Step6: Set DWrite high  , thus low it , and prepare to read the waveform.

  Well, I found in this case, the PLL was not locked, I am sure there was no problem with my SPI configuration process of DRS4. 

  toggle from DTAP could be viewed, but not stable. 

 Any Suggestions ?

  thanks.

  92   Fri Jun 18 11:45:18 2010 Stefan RittDVDD Problem of DRS 4

Jinhong Wang wrote:

 

 Hi Stefan

       I designed the evaluation board for our experiment. On our boards, I  encountered the similar problem when working on the PLL of DRS4. I compared the following two configuration process, which on with PLL locked, the other not,

   Process1: 

       step 1: Set DEnable and DWrite low, 

      Step2 : Reset DRS4 with a negative pulse of about 900 ns

      Step3: Set DEnable high,  thus do nothing but wait

       I found DRS4 PLL working and locked. 

  

  Process 2:

   Step 1: Set DEnable and DWrite low, 

  Step2 : Reset DRS4 with a negative pulse of about 900 ns 

  Step3: Set Config. Register( "11111111" .of course, this step was not necessary, just to see whether SPI was working properly from DTAP when set to "11111110")

  Step4: Set The read shift Register ( full read out mode)

  Step5: Set DEnable high, 

  Step6: Set DWrite high  , thus low it , and prepare to read the waveform.

  Well, I found in this case, the PLL was not locked, I am sure there was no problem with my SPI configuration process of DRS4. 

  toggle from DTAP could be viewed, but not stable. 

 Any Suggestions ?

  thanks.

So the main difference, if I understand correctly, is the setting of the Config Register. Actually I never tried that, I always went with the default settings (all "1"). What happens if you write "00000000"? You know Bit1 controls the PLL, maybe there is a bug and the signal needs to be inverted. 

  93   Sat Jun 19 10:09:18 2010 Jinhong WangDVDD Problem of DRS 4

Stefan Ritt wrote:

Jinhong Wang wrote:

 

 Hi Stefan

       I designed the evaluation board for our experiment. On our boards, I  encountered the similar problem when working on the PLL of DRS4. I compared the following two configuration process, which on with PLL locked, the other not,

   Process1: 

       step 1: Set DEnable and DWrite low, 

      Step2 : Reset DRS4 with a negative pulse of about 900 ns

      Step3: Set DEnable high,  thus do nothing but wait

       I found DRS4 PLL working and locked. 

  

  Process 2:

   Step 1: Set DEnable and DWrite low, 

  Step2 : Reset DRS4 with a negative pulse of about 900 ns 

  Step3: Set Config. Register( "11111111" .of course, this step was not necessary, just to see whether SPI was working properly from DTAP when set to "11111110")

  Step4: Set The read shift Register ( full read out mode)

  Step5: Set DEnable high, 

  Step6: Set DWrite high  , thus low it , and prepare to read the waveform.

  Well, I found in this case, the PLL was not locked, I am sure there was no problem with my SPI configuration process of DRS4. 

  toggle from DTAP could be viewed, but not stable. 

 Any Suggestions ?

  thanks.

So the main difference, if I understand correctly, is the setting of the Config Register. Actually I never tried that, I always went with the default settings (all "1"). What happens if you write "00000000"? You know Bit1 controls the PLL, maybe there is a bug and the signal needs to be inverted. 

 Hi, Stefan,

       The problem was fixed by setting Reg_addr "1001" instead of "1111" when in idle state, I was confused. 

  15   Fri Oct 16 09:51:03 2009 Jinhong WangDSR4 Full Readout Mode

Hello Mr. Stefan Ritt

          In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after 38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for the parallel mode,in which the multiplexer is not used?

          Best wishes!

                                                       Jinhong Wang

  16   Fri Oct 16 10:16:10 2009 Stefan RittDSR4 Full Readout Mode

Jinhong Wang wrote:

Hello Mr. Stefan Ritt

          In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after 38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for the parallel mode,in which the multiplexer is not used?

          Best wishes!

                                                       Jinhong Wang

The clock-to-output delay is the same if one uses the multiplexer or not. I found however that in most cases the delay of 38 ns needs some fine tuning to get optimal performance. So I typically use a shifted clock generated by the FPGA clock manager with a programmable delay (+-5 ns for Xilinx) and optimize this in the running system.

  14   Wed Oct 14 23:53:05 2009 Armin KolbDRS_exam using USB Evaluation Board with OS X

For the users using a Macintosh,

after several hours the Evaluation Board is working  on my Macintosh (intel).

1) install the development package with xcode, its on the OS X installation DVD

2) install the libusb binary from http://www.ellert.se/twain-sane/

3) modify the makefile  for compiling drs_exam (attached) afterwards it's running perfect!

 

best,

Armin

 

  307   Tue Nov 19 04:33:22 2013 Andriy ZatserklyaniyDRSOsc at Mac OS X Mavericks

 I installed Mac OS package on macbook (late 2013). DRSOsc starts to write file but freezes; need to be restarted to restore connection with DRS4 evaluation board (ordered Aug 2011). 

When I ran from the command line, I see these messages:

phone$ /Applications/DRSOsc.app/Contents/MacOS/DRSOsc

2013-11-18 15:11:31.278 DRSOsc[96539:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

2013-11-18 15:11:31.279 DRSOsc[96539:507] CoreText performance note: Set a breakpoint on CTFontLogSuboptimalRequest to debug.

2013-11-18 15:11:31.281 DRSOsc[96539:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

2013-11-18 15:11:31.283 DRSOsc[96539:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

2013-11-18 15:11:31.285 DRSOsc[96539:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

0 - 0.250

1 - 0.250

2 - 0.250

3 - 0.250

0 - 0.250

1 - 0.250

2 - 0.250

3 - 0.250

2013-11-18 15:11:32.933 DRSOsc[96539:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

...

...

 

and these:

 

musb_write: requested 10, wrote 0, errno -4 (Unknown error: -4)

musb_read error 0

musb_write: requested 10, wrote 0, errno -4 (Unknown error: -4)

musb_read error 0

...

...

 

I tried to compile Linux package, but got error messages:

 

drs-4.0.1$ make

cc -g -O2 -Wall -Wuninitialized -fno-strict-aliasing -Iinclude -I/opt/local/include -DOS_DARWIN -DHAVE_USB -DHAVE_LIBUSB10 -DUSE_DRS_MUTEX -c src/musbstd.c

cc -g -O2 -Wall -Wuninitialized -fno-strict-aliasing -Iinclude -I/opt/local/include -DOS_DARWIN -DHAVE_USB -DHAVE_LIBUSB10 -DUSE_DRS_MUTEX -c src/mxml.c

In file included from src/mxml.c:79:

include/strlcpy.h:27:14: error: expected parameter declarator

size_t EXPRT strlcpy(char *dst, const char *src, size_t size);

             ^

/usr/include/secure/_string.h:105:44: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:62: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                             ^

/usr/include/secure/_common.h:30:32: note: expanded from macro '_USE_FORTIFY_LEVEL'

#    define _USE_FORTIFY_LEVEL 2

                               ^

In file included from src/mxml.c:79:

include/strlcpy.h:27:14: error: expected ')'

/usr/include/secure/_string.h:105:44: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:62: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                             ^

/usr/include/secure/_common.h:30:32: note: expanded from macro '_USE_FORTIFY_LEVEL'

#    define _USE_FORTIFY_LEVEL 2

                               ^

include/strlcpy.h:27:14: note: to match this '('

/usr/include/secure/_string.h:105:44: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:53: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                    ^

In file included from src/mxml.c:79:

include/strlcpy.h:27:14: warning: type specifier missing, defaults to 'int' [-Wimplicit-int]

size_t EXPRT strlcpy(char *dst, const char *src, size_t size);

             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

/usr/include/secure/_string.h:105:44: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

                                           ^~~~~~~~~~~~~~~~~~~~

/usr/include/secure/_common.h:39:31: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                              ^~~~~~~~~~~~~~~~~~~~~

In file included from src/mxml.c:79:

include/strlcpy.h:27:14: error: conflicting types for '__builtin___strlcpy_chk'

/usr/include/secure/_string.h:105:3: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

  ^

include/strlcpy.h:27:14: note: '__builtin___strlcpy_chk' is a builtin with type 'unsigned long (char *, const char *, unsigned long, unsigned long)'

/usr/include/secure/_string.h:105:3: note: expanded from macro 'strlcpy'

  __builtin___strlcpy_chk (dest, src, len, __darwin_obsz (dest))

  ^

In file included from src/mxml.c:79:

include/strlcpy.h:28:14: error: expected parameter declarator

size_t EXPRT strlcat(char *dst, const char *src, size_t size);

             ^

/usr/include/secure/_string.h:111:44: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:62: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                             ^

/usr/include/secure/_common.h:30:32: note: expanded from macro '_USE_FORTIFY_LEVEL'

#    define _USE_FORTIFY_LEVEL 2

                               ^

In file included from src/mxml.c:79:

include/strlcpy.h:28:14: error: expected ')'

/usr/include/secure/_string.h:111:44: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:62: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                             ^

/usr/include/secure/_common.h:30:32: note: expanded from macro '_USE_FORTIFY_LEVEL'

#    define _USE_FORTIFY_LEVEL 2

                               ^

include/strlcpy.h:28:14: note: to match this '('

/usr/include/secure/_string.h:111:44: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

                                           ^

/usr/include/secure/_common.h:39:53: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                                                    ^

In file included from src/mxml.c:79:

include/strlcpy.h:28:14: warning: type specifier missing, defaults to 'int' [-Wimplicit-int]

size_t EXPRT strlcat(char *dst, const char *src, size_t size);

             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

/usr/include/secure/_string.h:111:44: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

                                           ^~~~~~~~~~~~~~~~~~~~

/usr/include/secure/_common.h:39:31: note: expanded from macro '__darwin_obsz'

#define __darwin_obsz(object) __builtin_object_size (object, _USE_FORTIFY_LEVEL > 1 ? 1 : 0)

                              ^~~~~~~~~~~~~~~~~~~~~

In file included from src/mxml.c:79:

include/strlcpy.h:28:14: error: conflicting types for '__builtin___strlcat_chk'

/usr/include/secure/_string.h:111:3: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

  ^

include/strlcpy.h:28:14: note: '__builtin___strlcat_chk' is a builtin with type 'unsigned long (char *, const char *, unsigned long, unsigned long)'

/usr/include/secure/_string.h:111:3: note: expanded from macro 'strlcat'

  __builtin___strlcat_chk (dest, src, len, __darwin_obsz (dest))

  ^

2 warnings and 6 errors generated.

make: *** [mxml.o] Error 1

 

 

What the best way to build DRSOsc on the Mac OS X?

 

Thanks,

Andriy.

  308   Tue Nov 19 09:09:01 2013 Stefan RittDRSOsc at Mac OS X Mavericks

Andriy Zatserklyaniy wrote:

I installed Mac OS package on macbook (late 2013). DRSOsc starts to write file but freezes; need to be restarted to restore connection with DRS4 evaluation board (ordered Aug 2011). 

DRSOsc seems broken on OSX 10.9. I'm working on this right now. Some of the problems are related to wxWidgets, so I'm waiting for a new version running stably under OSX 10.9. The compilation problem related to "strlcpy" comes from the fact that OSX 10.9 now comes with its own version of that function, while all previous versions did not. So simply removing strlcpy.h/c from the project fixes that.

There will be a new version of DRSOsc next month which fixes all this problems, so just stay tuned.

/Stefan 

  309   Tue Nov 19 21:49:37 2013 Andriy ZatserklyaniyDRSOsc at Mac OS X Mavericks

Stefan Ritt wrote:

Andriy Zatserklyaniy wrote:

I installed Mac OS package on macbook (late 2013). DRSOsc starts to write file but freezes; need to be restarted to restore connection with DRS4 evaluation board (ordered Aug 2011). 

DRSOsc seems broken on OSX 10.9. I'm working on this right now. Some of the problems are related to wxWidgets, so I'm waiting for a new version running stably under OSX 10.9. The compilation problem related to "strlcpy" comes from the fact that OSX 10.9 now comes with its own version of that function, while all previous versions did not. So simply removing strlcpy.h/c from the project fixes that.

There will be a new version of DRSOsc next month which fixes all this problems, so just stay tuned.

/Stefan 

 I will have beam test next week :-(

I installed wxWidgets-3.0 using MacPorts (and libusb too). After removing strlcpy and hacking of Makefile I managed to build MacOS application. 

 

When I launch DRSOsc.app/Contents/MacOS/DRSOsc from terminal, I see constantly pouring messages about fonts:

2013-11-19 12:21:22.232 DRSOsc[99520:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

2013-11-19 12:21:22.275 DRSOsc[99520:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

...

How may I get rid of them?

 

Another problem: I was not able to save data in binary (*.dat) file. I used DRSOsc settings to set binary format, I specified explicit extension *.dat, tried everything (including hiding extension), but was not able to save in binary format. Do I need to apply some trick? How may I hardcode usage of the binary format?

Thanks,

Andriy.

  310   Wed Nov 20 08:16:10 2013 Stefan RittDRSOsc at Mac OS X Mavericks

Andriy Zatserklyaniy wrote:

When I launch DRSOsc.app/Contents/MacOS/DRSOsc from terminal, I see constantly pouring messages about fonts:

2013-11-19 12:21:22.232 DRSOsc[99520:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

2013-11-19 12:21:22.275 DRSOsc[99520:507] CoreText performance note: Client called CTFontCreateWithName() using name "Lucida Grande" and got font with PostScript name "LucidaGrande". For best performance, only use PostScript names when calling this API.

Another problem: I was not able to save data in binary (*.dat) file. I used DRSOsc settings to set binary format, I specified explicit extension *.dat, tried everything (including hiding extension), but was not able to save in binary format. Do I need to apply some trick? How may I hardcode usage of the binary format?

The CoreText issue comes from WxWidgets or a combination with OSX 10.9. Many other people have the same problem:

https://bugzilla.mozilla.org/show_bug.cgi?id=934261

and I have no idea how to get rid of it.

Concerning your problem with the binary format, just have a look at elog:272

 

  180   Thu Oct 4 20:50:36 2012 Zach MillerDRS5

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

  181   Thu Oct 4 20:59:18 2012 Stefan RittDRS5

Zach Miller wrote:

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

You mix up two things: The DRS5 chip is a new device with improved samling speed (10 GSPS) and lower dead time. This chip might come in 2-3 years. The 16-input board you mentioned is a DAQ board based on the DRS4 chip. This board well be operational beginning of 2013 as a prototype. It is not clear however at this point in which way this board will be made available for public. Maybe we will license this to industry. The design is however pretty much defined: 16 channels with gain 0.1-100, 1 GHz Bandwidth, Gigabit Ethernet output, and multi-board capabilities. Trigger on each channel with logical combinations. 80 MSPS continuous sampling (in addition to the DRS4 sampling). Each channel can be biased 0-210 V for SiPMT or APD power. A 19" 3 HE crate will host 16 boards with 256 channels.

/Stefan

  182   Thu Oct 4 21:07:27 2012 Zach MillerDRS5

Stefan Ritt wrote:

Zach Miller wrote:

Hi,

Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release date?"

Thanks for your time,

Zach Miller

You mix up two things: The DRS5 chip is a new device with improved samling speed (10 GSPS) and lower dead time. This chip might come in 2-3 years. The 16-input board you mentioned is a DAQ board based on the DRS4 chip. This board well be operational beginning of 2013 as a prototype. It is not clear however at this point in which way this board will be made available for public. Maybe we will license this to industry. The design is however pretty much defined: 16 channels with gain 0.1-100, 1 GHz Bandwidth, Gigabit Ethernet output, and multi-board capabilities. Trigger on each channel with logical combinations. 80 MSPS continuous sampling (in addition to the DRS4 sampling). Each channel can be biased 0-210 V for SiPMT or APD power. A 19" 3 HE crate will host 16 boards with 256 channels.

/Stefan

 Thanks, Stefan. That was the information we were looking for.

Cheers.

-Zach

  154   Wed Feb 22 11:36:51 2012 sonalDRS4- analog pulse counting

Hello Sir,

Regarding to analog pulse counting by using DRS4 Rev.2.0 board, you have said that "There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months."

I am interested in it. I have DRS4 Rev.2.0 board. I have FPGA and Microcontroller firmware for this board. How can I implement this concept of counting pulses?

 


  155   Fri Feb 24 15:52:43 2012 Stefan RittDRS4- analog pulse counting

sonal wrote:

Hello Sir,

Regarding to analog pulse counting by using DRS4 Rev.2.0 board, you have said that "There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months."

I am interested in it. I have DRS4 Rev.2.0 board. I have FPGA and Microcontroller firmware for this board. How can I implement this concept of counting pulses?

 

As I said above, you need a V4 board which has the four hardware comparators mounted. You cannot do that with the V2 board, even with a firmware upgrade.

The firmware upgrade for the V4 board is not yet ready and I won't have time for that in the next 3-4 weeks, but afterwards maybe.

Best regards,

Stefan 

  156   Wed Feb 29 06:46:47 2012 SonalDRS4- analog pulse counting

Stefan Ritt wrote:

sonal wrote:

Hello Sir,

Regarding to analog pulse counting by using DRS4 Rev.2.0 board, you have said that "There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months."

I am interested in it. I have DRS4 Rev.2.0 board. I have FPGA and Microcontroller firmware for this board. How can I implement this concept of counting pulses?

 

As I said above, you need a V4 board which has the four hardware comparators mounted. You cannot do that with the V2 board, even with a firmware upgrade.

The firmware upgrade for the V4 board is not yet ready and I won't have time for that in the next 3-4 weeks, but afterwards maybe.

Best regards,

Stefan 

 Thank you for your response.

The DRS4 Rev.2.0 with one Multiplexer and a Comparator I think may be is ok for me. Since I wanted to implement counter in FPGA, I have gone through firmware but its very difficult for me to get the flow of data from DRS to USB. Could you help me to get familiar with or to get flow of the data from DRS to the USB?

 

Thank You,

Sonal

  157   Thu Mar 1 19:22:26 2012 Stefan RittDRS4- analog pulse counting

Sonal wrote:

The DRS4 Rev.2.0 with one Multiplexer and a Comparator I think may be is ok for me. Since I wanted to implement counter in FPGA, I have gone through firmware but its very difficult for me to get the flow of data from DRS to USB. Could you help me to get familiar with or to get flow of the data from DRS to the USB?

Hi Sonai,

unfortunately I cannot teach you VHDL, you should take a course somewhere. Actually you don't have to touch the USB part, you just have to implement a new register in the firmware, and connect it to a VHDL counter attached to the trigger input. I will do this in a couple of weeks myself, so you can also just wait. I will however only do this for the V4 board, so you have to port it back to the V2 firmware.

Best regards,

Stefan

Goto page Previous  1, 2, 3 ... 33, 34, 35 ... 43, 44, 45   Next  
ELOG V3.1.5-2eba886