 Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width
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Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal
routing on the DRS4 chip.
Stefan |
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Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support
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I put that on the wish list, but I won't have time for that in the next months.
Stefan
Martin |
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Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
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Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
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Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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The "Trigger OUT" has changed recently. It goes high on a new trigger, but then STAYS high until the board has been read out by the PC and
re-started. This allows better synchronization with some external trigger, which can be re-armed with the falling edge of the trigger out signal. The signal
can be quite long, since readout of an event via USB typically takes 2 ms, but can be more if the PC is busy. If you need back your 150 ns pulse, |
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Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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In meantime I even updated the manual.
Stefan
Gerard |
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Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
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The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
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Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
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That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
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Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
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Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software
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This one elog:361 should still work.
Stefan
Abaz |
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Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s)
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The reduction of rate is because you save in XML format, which is an ASCII format, so human readable, but takes long to write. If you switch to binary
format and write on a decent fast hard disk, you should get back to 450 Acq/s.
Stefan |
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Mon Feb 4 16:46:04 2019, Stefan Ritt, Different Distances between the sampling points
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The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might
have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width,
you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins. |
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Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points
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elog:361
Hans
Steiger wrote:
Sorry.... but is there a solution or a Root Macro, that reads the |
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Wed Feb 20 08:08:42 2019, Stefan Ritt, meg?
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You have to change the path to libusb-1.0.lib to the one where you installed it.
Stefan
Lev |
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Wed Feb 20 12:56:56 2019, Stefan Ritt, meg?
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No idea. Maye some access problem. Have you tried to start your program under an admin account?
Stefan
Lev |
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Thu Feb 21 09:57:53 2019, Stefan Ritt, no board found
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Could be. Have you tried that elog:657
Stefan
Lev |
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Mon Feb 25 08:48:27 2019, Stefan Ritt, no board found
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"dynamic" or "static" does not matter, as long as you don't use your program on another computer. I have no more idea about the
"no board found" problem. It works ok on all computers I tried at our lab.
Stefan |
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Fri Apr 12 09:55:50 2019, Stefan Ritt, multi-board
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Subtract 16 ns from your measured value ;-)
Stefan
Lev |
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Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board
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If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway.
So a proper timing calibration is not a crutch.
What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between |
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Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state
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Dear Andrew,
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately
the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline |