 Wed Feb 11 12:21:07 2009, Stefan Ritt, Corrected datasheet Rev. 0.8
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Please note the new datasheet Rev. 0.8 available from the DRS web site. It fixes the label of pin #76, which was AGND but is actualy AVDD. The
input IN8+ is located at pin #20 and not at pin #19 as described in the old table 2. |
Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0? 
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In the equations for computing the corrected time for channels other than channel 1, does anyone know what the term t0,0 refers
to? This is the last term in the last equation on page 24 of DRS4 Evaluation Board User’s Manual, Board Revision 5 as of January 2014, Last
revised: April 27, 2016. |
 Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0?
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t0,0 refers to the time of cell #0 of channel #0. So basically you keep channel 0 fixed, calculate the difference of each channel's cell #0 in respect
to channel 0, and align all channels except channel 0 so that their cell #0 has the same value. There is an inconsistency between the channel numbering.
The formula uses 0...3 and the manual says "channel 1" but it means actually the first channel, which uses index "0". |
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Tue Jan 12 17:57:03 2016, Jack Bargemann, Compiling DRS-exam
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I am trying to compile drs-exam, but am getting an error message I do not understand:
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_open referenced in function _musb_open
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_close referenced in function _musb_close |
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Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam
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I guess you are compiling under MS Windows ??? You probably don't link correctly to the USB lib. Try to compile the examples coming with libusb-1.0
to make you everything is right there.
Jack |
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Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ
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Hi,
I'm currently working on a little DAQ system with four DRS evaluation boards. Do i need to apply any specific settings when using the clock in/out
connectors for synchronization? I do not see anything like that in the drs_exam_multi example. |
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Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ
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Simon Weingarten wrote:
Hi, |
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Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ
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Stefan Ritt wrote:
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Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ
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Here is the full version of the program with clock daisy-chaining. Before switching to the external clock, it checks if the clock really
is there (by reading an internal scaler), and only then enables it. Note that the code also works without clock daisy-chaining. But without clock daisy-chaining
your have some 400 ps time resolution between boards, and with clock daisy-chaining you get some 60 ps. |
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Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ
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Hi Stefan,
do you know how these numbers (400ps and 60ps) scale with the sampling rate? The manual says they are for 5GS/s, do they change with slower sampling?
Thanks and best regards, |
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Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ
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The resolution coming from the sampling rate goes into these numbers, but just marginally. At 5 GSPS, you get a few ps reolution, while at 1 GSPS, you
get like 15 ps. If you convolve 15 ps with 400 ps, you get 400.3 ps, which is not significantly worse than 400 ps.
Simon |
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Thu May 8 23:23:19 2025, Jonathan Bradshaw, Clarification of full channel readout
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Hi all
We're working on a new product using the DRS4 IC, and want to do a full readout from cell 0 (not just Region of Interest). I have a
couple of questions I hope you can help me with: |
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Fri May 9 08:26:17 2025, Stefan Ritt, Clarification of full channel readout
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The full readout mode is not really recommended since you have to pull out the stop position separately. Just do the ROI readout using the RSRLOAD signal,
and then do 1024 samples, which also gives you the full waveform, but also the stop position in a single readout cyclce. The "full readout mode"
is more there for "historical reasons", but nobody really uses it any more. |
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Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error
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When starting Chip Test in DRS Command Line Interface, I receive the following message:
Cell error on channel 1, cell 5: -154.4 mV instead 0 mV
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Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error
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Georg Winner wrote:
When starting Chip Test in DRS Command Line Interface, I receive the following message: |
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Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime()
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Hello,
I have a question about the GetTime() method in DRS.cpp. I understand how the DT values are applied for all channels, and I also understand
from the evaluation board manual that the timing of each channel is synchronized at sample 0, so samples should really be aligned from channel-to-channel |
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Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()
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Cell 700 is arbitrary. You can choose any cell to align the channels to each other. The only requirement is that it's always the same cell for each
event. Historically, Daniel chose cell #700 more or less arbitrary, but later we found out that this works with any cell. So for the publication we went
with cell #0 (and that's why we have t_ch,0 in the paper), but cell #700 was left in the code because of lazyness. Feel free to replace 700 with any |
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Sat Oct 22 13:24:20 2022, Phan Van Chuan, Channel Cascading Option in the 2048-bin
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Dear Stefan,
We are using DRS4 evaluation board version 5.1 and firmware version 30000 (as the picture attached). Now, I am in need one channel with length 2048
bin. However, I can't find the resistors R99, ... ,R106 on the hardware of evaluation board; it seems my DRS4 evaluation board doesn't use 2048 |
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Mon Oct 24 12:50:24 2022, Stefan Ritt, Channel Cascading Option in the 2048-bin
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The board is delivered in one or the other mode and not meant to be changed by the user, since this requires very delicate soldering which is not easy.
If you try anyhow, you loose the quarantee. You can send the board back to the manufacturer for the modification, but this costs quite some moeny.
Best regards, |
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Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading
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Dear All,
I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing
pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, |