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Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing        Wed Dec 20 15:30:38 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp        Wed Dec 20 16:30:45 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp    Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width    Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing        Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing    Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs    Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5        Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5        Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5    Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform    Thu Oct 6 15:23:18 2016, Will Flanagan,     Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps?    Wed Apr 16 03:22:43 2014, Wang , why is the first channel output error?     Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong.        Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10    Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output        Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output    Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset         Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset

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