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+    Sun Apr 3 22:34:28 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal     +    Sat Apr 2 11:41:07 2016, Stefan Ritt, Question about timimng calibration     +    Tue Mar 22 12:54:41 2016, Stefan Ritt,      +    Mon Feb 29 13:09:29 2016, Stefan Ritt, baseline shift     +    Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data     +    Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode     +    Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec     +    Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam     +    Tue Jan 12 16:06:07 2016, Stefan Ritt, Use of Channel Cascading in drs_exam.cpp     +    Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7     +    Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5    Wed Oct 7 13:06:34 2015, Ilja Bekman, Voltage Calibration with signal on the input    Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS     +    Fri Aug 7 20:32:15 2015, Felix Bachmair, DRS4     +    Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples     +    Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files     +    Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz     +    Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1     +    Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application     +    Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints

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