DRS4 Forum
  DRS4 Discussion Forum, all entries  Not logged in ELOG logo
   +  Reply  Tue May 26 12:44:16 2020, Stefan Ritt, Domino wave Screenshot_2020-05-26_at_12.43.40_.png
   +  Reply  Mon May 25 03:36:12 2020, Keita Mizukoshi, DRS4 Evaluation board control tool 'drscl' with macro file 
   +  Reply  Fri May 22 13:24:51 2020, Stefan Ritt, Type check at DOFrame.h in official software 
Entry  Mon Mar 23 15:03:28 2020, Ajay Krishnamurthy, USB trigger issue 
   +  Reply  Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0? 
   +  Reply  Tue Oct 15 08:14:17 2019, Danyang, how to acquire the stop position with channel cascading 
Entry  Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time 
   +  Reply  Tue Aug 27 09:14:03 2019, Stefan Ritt, DRS4 
   +  Reply  Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register? 
   +  Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
   +  Reply  Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality 
   +  Reply  Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
   +  Reply  Wed Jun 26 15:17:51 2019, Si Xie, Running drs_example.cpp 
   +  Reply  Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state 
   +  Reply  Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board 
Entry  Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit 
Entry  Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software read_binary.C
Entry  Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs 
   +  Reply  Mon Feb 25 08:48:27 2019, Stefan Ritt, no board found 
   +  Reply  Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points 
   +  Reply  Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s) 
   +  Reply  Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software 
   +  Reply  Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study 
   +  Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
   +  Reply  Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs? 
   +  Reply  Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
   +  Reply  Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed 
   +  Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
   +  Reply  Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support 
   +  Reply  Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing 
   +  Reply  Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width 
   +  Reply  Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed 
   +  Reply  Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage 
   +  Reply  Fri Jun 8 08:11:05 2018, Stefan Ritt,  
   +  Reply  Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED 
   +  Reply  Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components 
   +  Reply  Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces 
   +  Reply  Sun May 6 11:45:09 2018, Stefan Ritt, confusion about the description in drs.cpp 
   +  Reply  Fri May 4 11:56:08 2018, Stefan Ritt, Voltage and Timing Calibration in drs_exam.cpp 
   +  Reply  Wed May 2 09:24:53 2018, Stefan Ritt, DRS4 using drs_exam.cpp to save as binary files 
   +  Reply  Tue Apr 17 13:28:23 2018, Stefan Ritt, DRS4 read_binary.cpp  
   +  Reply  Fri Mar 23 09:39:55 2018, Stefan Ritt, Read the CalibrateWaveform 
   +  Reply  Mon Mar 19 16:22:42 2018, Stefan Ritt, ROI  
   +  Reply  Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps? 
   +  Reply  Tue Feb 27 18:12:32 2018, Stefan Ritt, DRS4 Dead times 
   +  Reply  Thu Jan 25 08:07:32 2018, chen wenjun, problem with the drscl(drs507) 
   +  Reply  Thu Jan 25 06:10:52 2018, chen wenjun, drscl doesn't find eval board but drsosc does (Windows 7) 
   +  Reply  Wed Jan 17 10:09:09 2018, Stefan Ritt, The input signals recorded are different with the signal showed in oscilloscope  
   +  Reply  Wed Dec 20 22:14:35 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
   +  Reply  Tue Dec 12 13:58:06 2017, Stefan Ritt, External trigger using Raspberry Pi 
   +  Reply  Wed Nov 22 14:52:31 2017, Stefan Ritt, Averaging capabilities  
   +  Reply  Wed Nov 22 09:19:11 2017, chen wenjun , using of the DRS Command Line Interface 
   +  Reply  Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND 
   +  Reply  Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset  
   +  Reply  Mon Oct 16 15:35:22 2017, Stefan Ritt, Raspberry Pi Connection Failure 
   +  Reply  Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing 
Entry  Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support 
   +  Reply  Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output 
   +  Reply  Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10 
   +  Reply  Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards 
   +  Reply  Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND) 
   +  Reply  Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels 
   +  Reply  Tue May 30 21:22:10 2017, Esperienza Giove, Setting input range 
   +  Reply  Fri May 26 08:48:25 2017, Stefan Ritt, Invalid magic number 0000 
   +  Reply  Thu Apr 20 06:30:13 2017, Strahinja Lukic, Wave rotation during transfer from the board? 
   +  Reply  Thu Apr 13 17:10:58 2017, Christian Farina, Stand-alone Time Calibration for PSI Board 
   +  Reply  Tue Apr 11 09:41:44 2017, Stefan Ritt, drs4 registers behaviour 
   +  Reply  Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses 
   +  Reply  Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl 
   +  Reply  Tue Jan 31 08:40:04 2017, Stefan Ritt, LLD and ULD discriminations, 
   +  Reply  Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems  
   +  Reply  Fri Jan 13 13:50:10 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3 
   +  Reply  Fri Dec 9 04:17:46 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data 
   +  Reply  Fri Dec 2 16:47:37 2016, Stefan Ritt, DRS4 Initiation 
   +  Reply  Wed Nov 30 10:45:29 2016, Stefan Ritt, Long timing between two channels 
   +  Reply  Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock 
   +  Reply  Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime() 
   +  Reply  Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView 
   +  Reply  Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro 
   +  Reply  Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header 
   +  Reply  Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line 
Entry  Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
   +  Reply  Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
Entry  Thu Oct 6 15:23:18 2016, Will Flanagan,  
   +  Reply  Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform 
   +  Reply  Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting 
   +  Reply  Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly? 
Entry  Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals 
   +  Reply  Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4 
Entry  Sun Jun 12 08:49:54 2016, Michael, problems of DRS4 
   +  Reply  Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ?? 
   +  Reply  Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events 
   +  Reply  Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download 
Entry  Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4 piedestaux_per_time.jpg
   +  Reply  Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each 
Entry  Thu Apr 28 15:47:53 2016, Stefan Ritt, New software version and binary format 
   +  Reply  Thu Apr 28 15:46:34 2016, Stefan Ritt, Best settings for time measurements 
   +  Reply  Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem  
   +  Reply  Tue Apr 26 13:42:42 2016, Stefan Ritt, DRS4 purchase information 
   +  Reply  Tue Apr 26 09:54:16 2016, Stefan Ritt, Negative fCellDT values from GetTimeCalibration() 
   +  Reply  Wed Apr 6 09:46:10 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run  
   +  Reply  Sun Apr 3 22:34:28 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
   +  Reply  Sat Apr 2 11:41:07 2016, Stefan Ritt, Question about timimng calibration 
   +  Reply  Tue Mar 22 12:54:41 2016, Stefan Ritt,  
   +  Reply  Mon Feb 29 13:09:29 2016, Stefan Ritt, baseline shift 
   +  Reply  Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data 
   +  Reply  Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode edge.png
   +  Reply  Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec 
   +  Reply  Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam 
   +  Reply  Tue Jan 12 16:06:07 2016, Stefan Ritt, Use of Channel Cascading in drs_exam.cpp 
   +  Reply  Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7 
   +  Reply  Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5 
Entry  Wed Oct 7 13:06:34 2015, Ilja Bekman, Voltage Calibration with signal on the input 
Entry  Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS 
   +  Reply  Fri Aug 7 20:32:15 2015, Felix Bachmair, DRS4 
   +  Reply  Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples 
   +  Reply  Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files Makefile
   +  Reply  Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz 
   +  Reply  Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1 
   +  Reply  Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application 
   +  Reply  Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints  
   +  Reply  Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB 
   +  Reply  Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage 
   +  Reply  Wed May 13 08:19:53 2015, Stefan Ritt, Getting Trigger Source 
Entry  Wed May 13 01:07:36 2015, Cosmin Deaconu, DRS4 Evaluation Board + Powered USB Hub 
   +  Reply  Tue Apr 21 13:06:39 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
   +  Reply  Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource 
   +  Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
   +  Reply  Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program 
Entry  Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root 
   +  Reply  Fri Jan 16 14:12:19 2015, Stefan Ritt, Mac OSX Yosemite 10.10 
   +  Reply  Tue Nov 25 14:06:34 2014, Stefan Ritt, Raspberry Pi drsosc does not exit properly 
Entry  Sun Oct 19 14:36:54 2014, Chris Tully, coverting the xml file format into binary 
   +  Reply  Thu Oct 16 16:16:12 2014, Stefan Ritt, binary files time calibration header in drs-5.0.2 
   +  Reply  Thu Oct 16 16:15:16 2014, Stefan Ritt, binary files with more than 4 drs board ver. 5.0.2 
   +  Reply  Tue Oct 14 16:51:37 2014, Stephane Debieux, USB Microcontroller firmware 
   +  Reply  Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail 
   +  Reply  Mon Sep 22 14:52:21 2014, Stefan Ritt, compilation error for v5.0.2 
   +  Reply  Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer 
   +  Reply  Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables 
   +  Reply  Wed Jul 30 17:05:38 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 
   +  Reply  Wed Jul 30 17:05:06 2014, Stefan Ritt, ROOT program to decode binary data from DRSOsc read_binary.Cread_binary.cpp
Entry  Wed Jul 30 11:38:58 2014, Tsutomu Nagayoshi, Sampling speed of DRS4 Board ver4 
   +  Reply  Wed Jul 16 12:10:19 2014, Stefan Ritt, change cascading from 1024 to 2048 bins for each input channel 
   +  Reply  Mon Jun 16 15:35:59 2014, Osip Lishilin, Announcement of new Evaluation Board V5 
   +  Reply  Thu Jun 12 17:16:13 2014, Stefan Ritt, CalibrationWaveform 
   +  Reply  Thu Jun 12 12:46:00 2014, Stefan Ritt, DRS eval bord v5 Timing 
   +  Reply  Tue May 27 16:07:17 2014, Stefan Ritt, Spikes in DRS4 data on custom baord. 
   +  Reply  Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode? 
   +  Reply  Thu Apr 24 23:03:25 2014, Carlo Stella, drs_exam project fail to compile 
Entry  Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong. QQ??20140417174309.jpg
   +  Reply  Wed Apr 16 10:24:55 2014, Stefan Ritt, DRS4 Evalboard V5 with Windows7Pro64bit 
   +  Reply  Wed Apr 16 08:30:32 2014, Stefan Ritt, why is the first channel output error?  
   +  Reply  Thu Mar 6 11:12:44 2014, Stefan Ritt, Software drs-5.0.0 fails to compile (drsosc) 
   +  Reply  Wed Feb 5 13:41:42 2014, Stefan Ritt, Repeated time calibration 
   +  Reply  Wed Jan 15 17:37:21 2014, Stefan Ritt, DRS4 installation on Windows 8 issues 
   +  Reply  Wed Jan 15 17:11:14 2014, Stefan Ritt, Some bug fixes and questions 
   +  Reply  Wed Jan 15 15:48:55 2014, Stefan Ritt, USB connection stops 
   +  Reply  Thu Jan 9 11:02:46 2014, Stefan Ritt, v5 software with v4 board calibration 
   +  Reply  Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis 
   +  Reply  Fri Dec 13 11:37:58 2013, Stefan Ritt, input protection in DRS4 evaluation board 
   +  Reply  Tue Dec 10 14:54:46 2013, Stefan Ritt, measurement range 
   +  Reply  Tue Nov 26 15:38:13 2013, Stefan Ritt, reducing sampling speed 
   +  Reply  Thu Nov 21 14:45:56 2013, Stefan Ritt, Cascading of channels  
   +  Reply  Wed Nov 20 08:16:10 2013, Stefan Ritt, DRSOsc at Mac OS X Mavericks 
   +  Reply  Mon Nov 18 11:20:15 2013, Dmitry Hits, flickering screen for drsosc 
   +  Reply  Wed Nov 6 16:35:42 2013, Stefan Ritt,  
Entry  Mon Oct 21 14:43:21 2013, Stephane Debieux, DRS4 analog outputs - interfacing DRS4 to AD9222 ADC 
   +  Reply  Mon Sep 23 09:51:48 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board 
   +  Reply  Mon Aug 12 22:18:39 2013, Stefan Ritt, add an average ability to the Scope 
   +  Reply  Thu Jul 25 01:31:29 2013, Andrey Kuznetsov, Evaluation Board Behavior 
   +  Reply  Tue Jul 9 14:00:49 2013, Dmitry Hits, cannot save in binary format 
   +  Reply  Sat Jul 6 06:10:38 2013, Stefan Ritt, Missing methods in drs-4.0.1.tar.gz 
   +  Reply  Sat May 25 21:03:22 2013, Stefan Ritt, DRS4- analog pulse counting 
   +  Reply  Sat May 25 12:45:46 2013, Enrico Conti, mac osx 10.6 
   +  Reply  Mon Apr 22 15:52:53 2013, Stefan Ritt, effect of jitter/alignment between SRCLK and ADC clock adc_phase.jpg
   +  Reply  Fri Apr 12 08:38:17 2013, Stefan Ritt, code/details for optimal DRS4 timing calibration? 
Entry  Mon Apr 8 18:11:02 2013, Dmitry Hits, binary to root 
   +  Reply  Thu Apr 4 11:21:04 2013, Stefan Ritt, Differences in Source Code 
   +  Reply  Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error 
   +  Reply  Thu Feb 28 12:58:44 2013, Stefan Ritt, clock and trigger outs 
   +  Reply  Fri Feb 22 11:56:57 2013, Stefan Ritt, DRS4 trigger, different polarity 
   +  Reply  Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling 
   +  Reply  Tue Feb 5 14:38:35 2013, Stefan Ritt, variation of sampling capacitors 
   +  Reply  Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example 
   +  Reply  Fri Dec 14 10:07:54 2012, Evgeni, DRS-4 trigger 
   +  Reply  Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using 
   +  Reply  Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards. 
Entry  Wed Nov 28 16:54:46 2012, Stefan Ritt, DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8 screenshot_pi.png
   +  Reply  Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board 
   +  Reply  Tue Nov 13 11:26:32 2012, Stefan Ritt, GetWave 
   +  Reply  Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware 
   +  Reply  Fri Oct 12 14:09:37 2012, Stefan Ritt, DRS abbreviation 
   +  Reply  Thu Oct 4 21:07:27 2012, Zach Miller, DRS5 
   +  Reply  Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
   +  Reply  Mon Aug 6 02:44:00 2012, Stefan Ritt, Calculation of loop filter parameters (R,C1and C1) for 1 GHz 
   +  Reply  Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows 
   +  Reply  Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels 
   +  Reply  Wed Apr 25 13:42:37 2012, Stefan Ritt, DRS4 Initialization 
Entry  Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors 
   +  Reply  Mon Feb 6 08:15:38 2012, Stefan Ritt, what sort of detectors for physical experiment the DRS4 used? 
Entry  Tue Jan 31 08:10:37 2012, Stefan Ritt, IEEE Real Time 2012 Call for Abstracts 
   +  Reply  Thu Jan 26 10:05:57 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
   +  Reply  Fri Jan 20 23:50:39 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4 
   +  Reply  Wed Dec 14 08:55:29 2011, Stefan Ritt, Synchronization Delay in the Firmware for 8051 Controller 
Entry  Mon Dec 12 16:43:04 2011, Stefan Ritt, DC coupled DRS4 input stage DRS4_front_end_DC.pdf
   +  Reply  Fri Dec 9 17:45:48 2011, Michael Büker, Fixes to DOScreen.cpp for recent built on linux 
   +  Reply  Tue Nov 1 11:07:02 2011, Stefan Ritt, How to link PMT 
   +  Reply  Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout 
   +  Reply  Sat Oct 22 00:40:02 2011, Stefan Ritt, DRS4 eval board: readout rate 
   +  Reply  Mon Sep 19 08:53:22 2011, Stefan Ritt, compilation error for version 4.0.0 on linux 
   +  Reply  Fri Sep 9 09:31:33 2011, Stefan Ritt, DRS4 and AD9222 
   +  Reply  Wed Jul 13 04:26:52 2011, Stefan Ritt, Fixed Patter Timing Jitter 
   +  Reply  Thu Jun 2 21:01:29 2011, Stefan Ritt, Removing spikes 
Entry  Fri Feb 25 10:13:51 2011, Stefan Ritt, Announcement digital pulse processing workshop 
   +  Reply  Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards 
   +  Reply  Tue Nov 16 16:38:06 2010, Stefan Ritt, Reference design for DRS4 active input buffer 
   +  Reply  Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS 
Entry  Mon Jul 12 16:07:37 2010, Stefan Ritt, Announcement evaluation board V3 eval3.png
   +  Reply  Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4 
   +  Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 
   +  Reply  Tue Jun 1 13:36:18 2010, Stefan Ritt, High Frequency Input for DRS 
   +  Reply  Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model 
   +  Reply  Thu May 6 08:15:39 2010, Stefan Ritt, Random noise spec in datasheet 
   +  Reply  Thu Apr 15 13:48:40 2010, Stefan Ritt, ROFS Configuration 
   +  Reply  Wed Apr 14 16:34:28 2010, Stefan Ritt, version 1.2 evaluation board with firmware 13279? 
   +  Reply  Tue Apr 13 14:15:16 2010, Stefan Ritt, Simple example application to read a DRS evaluation board 
   +  Reply  Tue Apr 13 13:56:07 2010, Stefan Ritt, Baseline Variation In Data 
   +  Reply  Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter 
   +  Reply  Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration 
   +  Reply  Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 
   +  Reply  Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip 
   +  Reply  Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data 
   +  Reply  Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit 
   +  Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Entry  Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010 
   +  Reply  Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output 
   +  Reply  Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello 
   +  Reply  Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM DRS.cppDRS.hdrs4_eval1.mcs
   +  Reply  Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp 
   +  Reply  Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4 
   +  Reply  Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4 qfn76.png
   +  Reply  Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4 
   +  Reply  Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4 
   +  Reply  Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode 
Entry  Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X Makefile
Entry  Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed no_res.png100ohm.png
Entry  Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability vdd_no_cap.pngvdd_470uf.png
Entry  Thu Jul 9 09:11:03 2009, Stefan Ritt, Current problems with drs_exam.cpp 
Entry  Tue Jul 7 16:39:57 2009, Stefan Ritt, Power up problem and remedy typical_mode.gif
Entry  Wed Jun 10 12:46:43 2009, Stefan Ritt, Input range switch added in Version 2.1.3 Capture.png
Entry  Mon Apr 27 15:09:49 2009, Stefan Ritt, Amplitude and Timing calibration for DRS4 Evaluation Board uncal.pngcal.png
Entry  Mon Feb 23 09:24:24 2009, Stefan Ritt, Rise-time measurements image001.jpgimage003.jpgsingle.jpg
Entry  Wed Feb 11 12:21:07 2009, Stefan Ritt, Corrected datasheet Rev. 0.8 
   +  Reply  Wed Jan 14 13:41:44 2009, Stefan Ritt, External Trigger Input requirements 
Entry  Mon Dec 15 13:37:38 2008, Stefan Ritt, Welcome 
ELOG V3.1.4-80633ba