ID |
Date |
Author |
Subject |
Text |
 |
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
|
723
|
Thu Nov 8 09:57:26 2018 |
Stefan Ritt | Pi attenuator on eval board inputs? | The attenuator compensates for the gain
of the buffer which is slightly above one.
In addition, it serves as a "placeholder" |
|
|
722
|
Mon Nov 5 17:17:08 2018 |
Sean Quinn | Pi attenuator on eval board inputs? | Dear DRS4 team,
I am curious about this part of |
|
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|
|
720
|
Wed Sep 26 18:28:20 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I really
appreciate your help.
Thanks! |
|
|
Draft
|
Wed Sep 26 18:25:07 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Thank you very much for the answer, I
really appreciate your help.
Thanks! |
|
|
718
|
Wed Sep 26 14:44:14 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | The "Trigger OUT" has changed
recently. It goes high on a new trigger,
but then STAYS high until the board has been |
|
|
717
|
Sun Sep 23 02:22:46 2018 |
Gerard Arino-Estrada | Trigger OUT pulse width variable from 100 us up to 100 ms | Hello Stefan,
I am using the DRS4 board connected
to a Raspberry PI and through the drsosc |
|
|
716
|
Thu Sep 13 18:09:13 2018 |
Martin Petriska | "Symmetric spikes" fixed | Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
|
|
715
|
Tue Sep 4 13:04:30 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Yes it's possible, but I have to find
time for that. The software of the evaluation
board takes care of the spikes ("remove |
|
|
714
|
Mon Sep 3 11:17:26 2018 |
Martin Petriska | "Symmetric spikes" fixed | Hi,
Is it possible to fix it by FPGA
changes? I see readout cycle (proc_drs_reedout) in |
|
|
713
|
Tue Aug 21 14:36:44 2018 |
Stefan Ritt | Optimal readout speed | The analog output of the DRS4 chip needs
some time to settle. In principle it need
an infinite amout of time (exponential curve) |
|
|
712
|
Tue Aug 14 06:10:49 2018 |
Stefan Ritt | Latch delay support | I put that on the wish list, but I won't
have time for that in the next months.
Stefan |
|
|
711
|
Mon Aug 13 19:44:59 2018 |
Martin Petriska | Latch delay support | Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, |
|
|
710
|
Wed Aug 1 00:49:30 2018 |
Sean Quinn | Optimal readout speed | Dear DRS4 team,
On page 3 of the data sheet, Table
1. for readout speed a typical value of 10 |
|
|
709
|
Fri Jul 20 00:44:13 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Just a follow-up update.
It turns out that I was using a
cubic spline interpolation with smoothing. |
|
|
708
|
Mon Jul 16 19:39:35 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Using a test pulse split into two channels
of the DRS4 Evaluation Board v5, I looked
at the time resolution using a leading edge |
|
|
707
|
Fri Jun 29 07:51:33 2018 |
Stefan Ritt | Negative Bin Width | Yes that's normal. A negative cell
bin width means that the next cell N+1 samples
the input signal before cell N. This can |
|
|
706
|
Thu Jun 28 19:55:45 2018 |
Woon-Seng Choong | Negative Bin Width | I am using a DRS4 Evaluation Board v5 and
running the drsosc.exe version 5.06 on
a Window 7 machine. I have performed the |
|