Tue Mar 1 19:03:37 2022, Keita Mizukoshi, Scaler issue to evaluate live time
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Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger. |
Thu Mar 3 16:14:16 2022, Stefan Ritt, Scaler issue to evaluate live time
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The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50
Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV |
Fri Mar 4 03:55:33 2022, Keita Mizukoshi, Scaler issue to evaluate live time ![pulse_example.png pulse_example.png](attachment.png)
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Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold). |
Mon Mar 7 16:37:54 2022, Stefan Ritt, Scaler issue to evaluate live time ![Screenshot_2022-03-07_at_16.37.32_.png Screenshot_2022-03-07_at_16.37.32_.png](attachment.png)
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I tried your measurement with the DRSOscilloscope app (see below), and I measure a constant difference of 10 Hz among the whole range of 100 Hz to 3
kHz.
So I don't know what's wrong on your side. Did you try with the oscilloscope app as well? Have you checked your pulse generator? The |
Sun Mar 6 17:54:47 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have connected 3 signals to the DRS4 Evaluation Board V5 which look like this in the drsosc app:
Note that here I am sampling at 5 GS/s. Using this app everything works perfect. |
Mon Mar 7 08:45:32 2022, Stefan Ritt, Why does not trigger at higher sampling frequencies?
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Unfortunately I have not idea what the problem could be. In principle the trigger should be independent of the sampling speed, since the trigger is only
made with a discriminator and a flip-flop. The hardware must be ok since you see the trigger with the oscillocope app. All you can do is to go through
the sorce code of the oscilloscope app, especially drsosc/Osic.cpp::ScanBoards(), SetTriggerLevel(), SetTriggerPolariy() etc. to make sure you do the same |
Tue Mar 8 00:25:56 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have seen in the app that the trigger source buttons do something different than the "or" and "transparent trigger" buttons:
If I enable the setup from the right, i.e. OR in CH4 and "Enable Transparent Trigger" the app stops triggering. This is the configuration |
Tue Mar 8 12:20:00 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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Sorry for the spam. Just want to let you know that I was able to solve the problem, it was all due to a `float` being casted as `int` in the Python binding.
Now it works like a charm.
Matias |
Fri Mar 11 17:26:15 2022, Matias Senger, Time calibration and the C++ API
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I am using the V5 board at a fixed sampling frequency. With the `drsosc` app I have executed the time calibration at 5 GS/s (actually 5.12 GS/s). This
is how my setup looks like in the app:
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Sat Mar 12 10:13:24 2022, Stefan Ritt, Time calibration and the C++ API
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DRSBoard::GetTime is declared in DRS.h line 720.
If you want to measure timing down to ps, you need some basic knowledge, especially about signal-to-noise and risetime. This cannot be taught
in a few sentenses, needs a full lecture. As a starting point please read that papat: |
Sat Mar 12 16:52:36 2022, Matias Senger, Time calibration and the C++ API
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Dear Stefan,
For the time of each bin I am using the values returend by `GetTime` without any assumption by my side. I did not notice before that the sampling
time is not uniform, but I see that this is already happening. This is an example plot from one of the signals I processed: |
Mon Mar 14 08:59:51 2022, Stefan Ritt, Time calibration and the C++ API ![Screenshot_2022-03-14_at_9.04.07_.png Screenshot_2022-03-14_at_9.04.07_.png](attachment.png)
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Looks like you have the some time calibration, not sure if it's the correct one. Sample the sine wave from the calibration clock, once with and once
without the timing calibration, then you will see if all points lie on a smooth line. Left: without timing calibration, right: with proper timing calibration:
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Tue Mar 15 13:07:50 2022, Matias Senger, Time calibration and the C++ API
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Thanks for your help. If I look into the app the behavior for the 4 channels is exactly as you show:
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Tue Apr 12 10:40:36 2022, LynseyShun,
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Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding
waveforms.
In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time? |
Tue Apr 12 10:49:27 2022, Stefan Ritt,
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A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works in our designs. Maybe double check the address lines with an oscilloscope.
Stefan
LynseyShun |
Thu Jun 16 05:31:25 2022, LynseyShun,
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Thank you very much for your help!
Stefan
Ritt wrote:
A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works |
Tue Jul 19 02:35:04 2022, Jingyu Zhang, Increase event rate, use ROI mode, and install sw from source in Mac
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Dear experts,
We are trying to increase the event rate of the DRS4. We looked into the ROI
but couldn’t figure out how to run in ROI mode. We are wondering if there is pre-existing firmware for this? We also tried to download and build |
Fri Jul 29 14:09:35 2022, Stefan Ritt, Increase event rate, use ROI mode, and install sw from source in Mac
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The firmware from the website always reads 1024 bins. You have to modify it to stop before that, like reading only 128 samples or so. For compiling under
MacOSX, this should work, since I do it myself.
Regards, |
Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings? ![spikes_16MHz.png spikes_16MHz.png](attachment.png) ![spike_period.png spike_period.png](attachment.png) ![better_spikes_15MHz.png better_spikes_15MHz.png](attachment.png)
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Dear DRS4 team,
I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy
data (post-calibration) with periodic spikes. |
Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?
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elog:824
Sean
Quinn wrote:
Dear DRS4 team, |
Fri Jun 24 09:57:36 2022, LynseyShun, Spikes/noise sensitive to clock settings?
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Hello, I now have periodic spikes in CH0 and CH1 output. How can I eliminate these spikes? I'm sorry I didn't understand your elimination
method. Please explain the method in detail. Thank you very much
Stefan |
Fri Jul 29 17:23:43 2022, Stefan Ritt, Spikes/noise sensitive to clock settings?
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Look at the DRS4 data sheet, Figure 12. You see there the rising SRCLK pulse which outputs the next analog value. You also see tSAMP which describes
the sampling piont (strobe or clock sent to your ADC). The value of tSAMP must be such that the values is sampled at the point where it flattens out, just
2-3 ns BEFORE the next analog sample is clocked out, as written in the text. So you have to phase shift your clock going to SRCLK and the one going to |
Wed Sep 7 10:13:41 2022, Prajjalak Chattopadhyay, Register status after reset
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What are the default register statuses after DRS4 gets reset? |
Tue Sep 27 10:17:58 2022, Kunal Shinde, Required Firmware for DRS4 Evaluation Board Version 2.0
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Hi, I am working on an old DRS4 board Version "2.0" with firmware revision "13191", I was unable to find this specific firmware source
files ("VHDL source code"), please help me where could I find this or send me the required.
Regards, |
Tue Sep 27 10:37:11 2022, Stefan Ritt, Required Firmware for DRS4 Evaluation Board Version 2.0
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You find each software version at the usual download location at
https://www.dropbox.com/home/drs/drs4/distribution/Download/Linux
The one you need is probably drs-2.1.3.tar.gz which was the last version for the 2.0 board which is now more than 10 years old. |
Tue Sep 27 10:52:41 2022, Kunal Shinde, Required Firmware for DRS4 Evaluation Board Version 2.0
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I checked the link you provided but it seems that the link doesnt exist please send me valid one.
Regards,
Kunal |
Tue Sep 27 15:20:55 2022, Stefan Ritt, Required Firmware for DRS4 Evaluation Board Version 2.0
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Sorry, got the wrong link. Here the right one: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
If you untar the archive, you will find a "firmware" subdirectory with all VHDL code.
Stefan |
Sat Oct 22 13:24:20 2022, Phan Van Chuan, Channel Cascading Option in the 2048-bin
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Dear Stefan,
We are using DRS4 evaluation board version 5.1 and firmware version 30000 (as the picture attached). Now, I am in need one channel with length 2048
bin. However, I can't find the resistors R99, ... ,R106 on the hardware of evaluation board; it seems my DRS4 evaluation board doesn't use 2048 |
Mon Oct 24 12:50:24 2022, Stefan Ritt, Channel Cascading Option in the 2048-bin
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The board is delivered in one or the other mode and not meant to be changed by the user, since this requires very delicate soldering which is not easy.
If you try anyhow, you loose the quarantee. You can send the board back to the manufacturer for the modification, but this costs quite some moeny.
Best regards, |
Mon Oct 17 16:29:37 2022, Sebastian Infante, DRS4 installation via tar in ubuntu not working
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Hello i cant install any the last versions that i downloaded from the dropbox, i can untar the file called drs-5.0.6 and when i type "make"
while inside the extracted folder that starts working properly till a point and i get an error, its worth mention that i installed wxWidgets and could
make a simple hello world that worked properly in wxWidgets. |
Mon Feb 6 13:28:28 2023, Stefan Ritt, DRS4 installation via tar in ubuntu not working
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I fixed the described error. Can you try the new version from https://bitbucket.org/ritt/drs4eb/commits/80b3af753ed32eb365725f0f3244a4109347c01b
Sebastian
Infante wrote:
Hello i cant install any the last versions that i downloaded from |
Fri Jun 9 04:11:40 2023, Javier Caravaca, Different sampling rates in multi-board configuration
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Hello,
Is it possible to have different sampling rates in multi-board configuration? I tried using the scope application but I am unable to change
the sampling rate independently. |
Mon Jun 12 14:22:04 2023, Stefan Ritt, Different sampling rates in multi-board configuration
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No, that's unfortunately not possible.
Stefan
Javier |
Wed Jun 10 12:46:43 2009, Stefan Ritt, Input range switch added in Version 2.1.3
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A new software verison for the DRS4 Evaluation Board has been has been released. Version 2.1.3 adds a switch for the input range of the DRS4 board.
Once can choose between -0.5V...0.5V and 0V...1V:
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Tue Sep 5 03:28:52 2023, Matias Henriquez, Input range switch added in Version 2.1.3
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Hello,
It is not quite clear to me yet how the input range is only determined by the front end and not the DRS4 chip. According to the datasheet, the
selection of ROFS determines whether the input differential range is -0.5V to 0.5V (ROFS=1.55V) or 0V to 1V (ROFS=1.05V) or -0.05V to 0.95V (ROFS=1.1V). |
Wed Sep 13 13:18:45 2023, Stefan Ritt, Input range switch added in Version 2.1.3
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To achieve an input range of -1V to 0V, you need an external buffer which can shift this range into the DRS4 range of -0.5V to +0.5V. This external buffer
has then to operate with bipolar power supplies, like -2.5V to +2.5V, which are not present on the evaluation board.
Best regards, |
Wed Oct 25 19:44:25 2023, John Westmoreland, WaveDREAM Design
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Hello All,
Are there any design resources available for the WaveDREAM PCBA's?
Thanks In Advance, |
Wed Oct 25 19:47:23 2023, Stefan Ritt, WaveDREAM Design
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No. This is a proprietary design.
Best,
Stefan |
Wed Oct 25 19:52:33 2023, John Westmoreland, WaveDREAM Design
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Stefan,
Oh, didn't realize that.
Thanks! |
Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA
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Hello:
A bit of background: I am working on a project that is utilizing the DRS4 Evaluation board as a prototype platform for a dedicated, special
use capture. We will only be utilizing one channel of the ADC capture, and the 1024 samples is more than enough. |
Thu Feb 22 10:37:03 2024, Stefan Ritt, Simulation of FPGA
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The Cypress has its own firmware, contained in the distribution under firmware/CY7C68013A/drs_eval.c. There you can see how the data is fetched. I kind
of forgot how exactly it worked, since I wrote that code back in 2011. But most if the Cypress code is just the configuration of the USB, the communication
with the FPGA is kind of straight forward in the Cypress implementation. But you have to read the manual of that chip to understand it. |