 Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling
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Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly sampled data?
Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga
Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel |
 Tue May 21 13:32:13 2013, Martin Petriska, mac osx 10.6
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> Hi,
>
> I would like to use the DRS4 with my macbook pro running osx 10.6.8.
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Thu Jan 9 10:58:19 2014, Martin Petriska, v5 software with v4 board calibration
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Hi
Question:
In v4 board, which channel has best calibration ? |
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Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables
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Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).
Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay
cable? |
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Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS
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There is software for DRS4 board and positron lifetime measurement availiable. Still in beta but works. Its usable for measuring time between
pulses in two or three channels and histogramming that time. (May be time of flight measurement should be tested too) Project code is here: http://sourceforge.net/projects/qtpals/.
More about it is here http://iopscience.iop.org/1742-6596/505/1/012044/. |
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Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data
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Robert
Adams wrote:
I would really love to be able to save histogram data, though I have |
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Wed Apr 6 09:01:28 2016, Martin Petriska, DRS Oscilloscope freezing after a long run
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Stefan
Ritt wrote:
I tried this night to run the board at a 10 Hz rate with an external |
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Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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I would like to implement fpga firmware changes for DRS4 eval board v4 to put there posibility for standard coincidence (for example to get triger
on two short (5ns pulses from Plastic scintilator) in 100ns coincidence window), Similar but more complex was done for eval v.5 boards ( https://forge.physik.rwth-aachen.de/projects/drs4-rwth
) Im beginner in state of FPGA design, but hope it will be not so dificult to implement same functionality in eval4 board. Is there any SVN server |
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Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support
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Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, but is it possible to add latch delay support to official firmware ? |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
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Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
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Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
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Tue Sep 5 03:28:52 2023, Matias Henriquez, Input range switch added in Version 2.1.3
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Hello,
It is not quite clear to me yet how the input range is only determined by the front end and not the DRS4 chip. According to the datasheet, the
selection of ROFS determines whether the input differential range is -0.5V to 0.5V (ROFS=1.55V) or 0V to 1V (ROFS=1.05V) or -0.05V to 0.95V (ROFS=1.1V). |
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Sat Feb 12 13:06:56 2022, Matias Senger, Cannot trigger on pulses, have to trigger on undershoot
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I am using the DRS4 board trying to measure pulses produced by an LGAD. I have no prior experience with this board, have just installed the `drsosc`
application and am exploring. I am experiencing some strange trigger behavior. Consider the following screenshot:
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Wed Mar 2 17:25:10 2022, Matias Senger, How to convert samples to volt?
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I am using the `drscl` app. My prior experience is practically zero, sorry if this is a very naive question. When I read using `read 0 1` (channel 0,
with calibration) I get this:
``` |
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Sun Mar 6 17:54:47 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have connected 3 signals to the DRS4 Evaluation Board V5 which look like this in the drsosc app:
Note that here I am sampling at 5 GS/s. Using this app everything works perfect. |
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Tue Mar 8 00:25:56 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have seen in the app that the trigger source buttons do something different than the "or" and "transparent trigger" buttons:
If I enable the setup from the right, i.e. OR in CH4 and "Enable Transparent Trigger" the app stops triggering. This is the configuration |
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Tue Mar 8 12:20:00 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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Sorry for the spam. Just want to let you know that I was able to solve the problem, it was all due to a `float` being casted as `int` in the Python binding.
Now it works like a charm.
Matias |
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Fri Mar 11 17:26:15 2022, Matias Senger, Time calibration and the C++ API
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I am using the V5 board at a fixed sampling frequency. With the `drsosc` app I have executed the time calibration at 5 GS/s (actually 5.12 GS/s). This
is how my setup looks like in the app:
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Sat Mar 12 16:52:36 2022, Matias Senger, Time calibration and the C++ API
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Dear Stefan,
For the time of each bin I am using the values returend by `GetTime` without any assumption by my side. I did not notice before that the sampling
time is not uniform, but I see that this is already happening. This is an example plot from one of the signals I processed: |
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Tue Mar 15 13:07:50 2022, Matias Senger, Time calibration and the C++ API
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Thanks for your help. If I look into the app the behavior for the 4 channels is exactly as you show:
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