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ID Date Author Subject Text   754   Fri Jun 21 12:54:47 2019 Stefan Ritt Evaluation firmware wait_vdd state   757   Wed Jun 26 13:08:42 2019 Stefan Ritt drs_exam is always reading out a sin wave   760   Mon Jul 8 14:29:12 2019 Stefan Ritt drs_exam is always reading out a sin wave   762   Mon Jul 15 17:26:50 2019 Stefan Ritt Evaluation Board Test Functionality   765   Thu Jul 18 11:37:56 2019 Stefan Ritt Trace Impedance   767   Sat Jul 20 12:28:14 2019 Stefan Ritt Trace Impedance   769   Tue Aug 20 10:44:45 2019 Stefan Ritt should one deassert DENABLE while writing the write-shift register?   772   Tue Aug 27 09:14:03 2019 Stefan Ritt DRS4   775   Mon Oct 14 10:14:46 2019 Stefan Ritt how to acquire the stop position with channel cascading   777   Mon Oct 14 12:56:13 2019 Stefan Ritt how to acquire the stop position with channel cascading   779   Mon Oct 14 15:27:09 2019 Stefan Ritt how to acquire the stop position with channel cascading   782   Fri Oct 25 16:39:07 2019 Stefan Ritt Computing corrected time from binary data...what is t_0,0?   786   Fri May 22 12:53:33 2020 Stefan Ritt DRS4 Evaluation board control tool 'drscl' with macro file   788   Fri May 22 13:24:51 2020 Stefan Ritt Type check at DOFrame.h in official software   791   Tue May 26 12:44:16 2020 Stefan Ritt Domino wave   794   Mon Aug 31 10:52:42 2020 Stefan Ritt Dynamic Range Evaluation Board and Software   796   Mon Aug 31 17:17:30 2020 Stefan Ritt Channel Cascading   798   Wed Oct 7 10:56:03 2020 Stefan Ritt External triggering   801   Tue Oct 27 13:37:23 2020 Stefan Ritt Timing diagram of SROUT/SRIN signal to write/read a write shift register   803   Tue Oct 27 15:24:38 2020 Stefan Ritt Timing diagram of SROUT/SRIN signal to write/read a write shift register

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