 Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces 
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Hi,
thank you for the quick reply. All the bins in the previous histograms have the same width. We also tried to plot the noise histogram for channel
2 with more bins (i.e. 1000, so that we can see almost discrete values), and the peak is still there. |
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Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces
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I tried the following:
- trigger on a 10 MHz sine wave on CH0, CH1 was open
- run drs_exam.cpp program and write data.txt with a few events |
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Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces
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Hi Stefan,
following your example, we tried to perform the same measurement, using drs_exam and taking 1000 events. The results we obtained are in the plots
attached (both in log and linear scale). We tried two different binnings: |
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Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces
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The DRS chip is read out with a 12 bit ADC, thus the phyical resolution is roughly 1V/4096 = 0.24 mV. I say roughly since the DRS has an analog gain
of 0.98, which is corrected for. Now you have integer values which are converted into floating point numbers my multiplying them with ~0.24mV. If you then
do histogramming with different bin sizes such as 0.1 mV and 0.35 mV , you get aliasing effects. The code truncates the result to 0.1 mV, which can give |
 Fri Feb 24 17:34:28 2017, Tarik Zengin, Passing parameters to drscl
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Hi everyone,
I wonder if there is a way to pass parameters to drscl. What I specifically want to do is calling drscl from a shell script and read/save some
data. I want to schedule a measurement. Therefore I need to call drscl from the command line using some parameters. |
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Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl
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This is indeed currently not implemented. But there is a simple C program drs_exam.cpp, which connects to a board and safes some data. You could modify
that program to your needs.
Stefan |
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Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
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Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |
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Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
Hi Stefan, |
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Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN |
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Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock
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Hello, everybody!
I installed DRSosc and DRScl. Command line works normally (at least, it can "see" the board). But when I start the oscilloscope, I
have an error: "PLLs did not lock on USB board #0, serial number #...". In Info section I can see the board type = 9 (and in the error message |
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Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock
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Which serial number has the board? Has it been in use before or is it a new board?
Stefan
Alexey |
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Mon Nov 28 16:48:15 2016, Alexey Lubinets, PLL did not lock
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The serial number is 2586. This board is about two years old, and it might be in use (but I do not know exactly).
Stefan
Ritt wrote:
Which serial number has the board? Has it been in use before or is it |
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Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock
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Have you tried to unplug and re-plug the board a few times? According to our database, you should have three boards. Do all three show the same behavior
or only this board? In case all three show this, it could be a hint of a software problem. If two boards are good and one is bad, this would be a hint
of a hardware problem (broken board). |
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Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration
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Hi Stefan,
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation |
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Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration
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Hao Huan wrote:
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. |