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ID Date Author Subject Text   907   Thu Feb 22 10:37:03 2024 Stefan Ritt Simulation of FPGA   913   Mon Jan 6 12:52:23 2025 Stefan Ritt Problem with C++ script to use DRS4 evaluation board. Not taking data.   915   Wed Mar 26 08:42:08 2025 Stefan Ritt drs_exam.cpp not compile   920   Fri May 9 08:17:50 2025 Stefan Ritt Handling of Write Shift Register and Write Config Register   921   Fri May 9 08:26:17 2025 Stefan Ritt Clarification of full channel readout   923   Tue May 13 08:51:34 2025 Stefan Ritt Handling of Write Shift Register and Write Config Register   926   Mon Jul 7 16:53:26 2025 Stefan Ritt Wrong Firmware Version: board has 13279, required is 15147. Board may not work properly   156   Wed Feb 29 06:46:47 2012 Sonal DRS4- analog pulse counting   679   Mon Apr 16 21:21:29 2018 Sobimpe Eniola DRS4 read_binary.cpp   386   Wed Oct 15 10:14:32 2014 Simon Weingarten Clock settings in daisy chain DAQ   388   Wed Oct 15 11:34:43 2014 Simon Weingarten Clock settings in daisy chain DAQ   403   Fri Apr 17 10:07:38 2015 Simon Weingarten Clock settings in daisy chain DAQ   551   Fri Oct 28 15:02:18 2016 Simon Mendisch Problems with DRS command line   756   Tue Jun 25 23:04:29 2019 Si Xie drs_exam is always reading out a sin wave   758   Wed Jun 26 15:10:09 2019 Si Xie drs_exam is always reading out a sin wave   759   Wed Jun 26 15:17:51 2019 Si Xie Running drs_example.cpp   800   Wed Oct 21 15:03:13 2020 Seiya Nozaki Timing diagram of SROUT/SRIN signal to write/read a write shift register   802   Tue Oct 27 15:02:09 2020 Seiya Nozaki Timing diagram of SROUT/SRIN signal to write/read a write shift register   804   Wed Oct 28 04:32:19 2020 Seiya Nozaki Timing diagram of SROUT/SRIN signal to write/read a write shift register   894   Mon Oct 17 16:29:37 2022 Sebastian Infante DRS4 installation via tar in ubuntu not working

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